Digital Phase Locked Loop

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此示例显示了如何使用混合信号模块™对数字相锁定循环进行建模。在数字相锁定环中，通过数字转换器（TDC）的时间执行相位检测，通过数字过滤器进行环滤波，振荡器是数字控制的振荡器（DCO）。该示例演示了TDC的行为模型，使用DSP Systen Toolbox™的BiquadFilter作为数字环路滤波器，并使用来自混合信号模块的VCO和DAC来对DCO进行建模。

This example also demonstrates one method for designing the control loop of a digital PLL by using the PLL architectures from the Mixed-Signal Blockset to design an analog PLL and then translate the analog design to its digital equivalent.

Digital PLL

Open and run the example model of a digital PLL. Then select the PLL Testbench in the model and click the Plot phase noise button (or call the button's callback function). Save loop filter waveform and phase noise data for later comparison to analog PLL results.

open('DigitalPLL.slx'); simout = sim(bdroot); msblks.PLL.pllTBPlotPhaseNoiseButton([bdroot'/PLL Testbench']);dpll_vcntl = simout.dpll_vcntl; getDigitalPllPhaseNoise;

数字转换器的时间

TDC的行为模型使用触发的子系统在参考时钟的上升边缘和PLL的分数划分器的上升边缘进行采样。然后，它计算了这两个采样时钟时间之间的差异，并将转换为八位整数输出值。为了建模由参考时钟时钟的数字反馈循环，将输出端口采样率设置为参考频率。

open_system（'DigitalPLL/TDC','force');

Digital Controlled Oscillator

The DCO model represents a circuit in which the control for a VCO is set by a digital to analog converter (DAC). The conversion in the DAC is triggered by the reference clock.

启用了VCO中的相位噪声障碍。DAC模型还可以对损伤进行建模。但是，在示例模型中未启用DAC损伤。

You could alternatively model a DCO by directly setting a Mixed-Signal Blockset VCO's control voltage array to an array of consecutive integers that spans the range of digital input values. Then you can set the output frequency array to supply the output frequency for each possible input value.

open_system（'DigitalPLL/DCO','force');

Digital Loop Filter

循环过滤器是DSP系统工具箱中的BiquadFilter。它是由TDC的输出端口以参考时钟频率计时的。

数字循环过滤器是使用自动设计功能设计的Integer N PLL with Single Modulus Prescalermodel from the Mixed-Signal Blockset PLL Architectures library. An analog loop filter is designed to achieve a specified loop bandwidth and phase margin, then the circuit values and sample interval are translated to digital filter coefficients. To obtain the correct overall loop gain, a scale factor is applied to the biquad filter model of the loop filter.

The derivation of the loop gain scale factor parallels that of基于电荷泵相锁环类比的全数字相锁定环的设计程序.

The variables used in the derivation are

$I_{CP}$ Charge pump maximum current amplitude
Analog loop filter transfer impedance
$k_ {vco}$ 对模拟和数字PLL的VCO敏感性
$T_{REF}$ Reference clock period
$\ delta_ {tdc}$ TDC time resolution
Digital loop filter transfer function
$k_ {dac}$ DAC收益

请注意，在此示例中，TDC的总范围是两个参考时钟周期。

The equation to make the loop gain of the analog and digital PLLs equal is:

${{{I_{CP}}} \over {2\pi }}Z\left( s \right){{{K_{VCO}}} \over s} = {{2{T_{REF}}} \over {{2_\pi }}}{1 \over {{\Delta _{TDC}}}}H\left( s \right){K_{DAC}}{{{K_{VCO}}} \over s}$

由于本示例中的TDC和DAC已配置为具有相同数量的位，因此该方程将减少为：

$h \ left（s \ right）= {{{i_ {cp}}}} \ aver 2} z \ left（s \ right）$

Since the functiongetSOSfromAnalogPLLincluded in this example produces filter coefficients that result in a filter gain $Z(s)$ , the scale factor for the loop filter is ${{{I_{CP}}} \over 2}$ .

While the loop filter coefficients, input signal and output signal in this example are all double precision floating point, it would also be possible to use Fixed-Point Designer™ to model the entire digital feedback path using exactly the same digital precision as in the circuit design, thus obtaining even more precise evaluation of impairments such as quantization noise.

You can design and configure the digital loop filter by running the script:

%%%designDigitalLoopFilter;

Compare to Analog PLL

您可以将模拟PLL与数字PLL的循环获取进行比较。模拟环滤波器响应中的附加高频涟漪是由于电荷泵波形。

open('AnalogPLL.slx'); simout = sim(bdroot); apll_vcntl = simout.apll_vcntl; plotLoopFilterWaveforms; msblks.PLL.pllTBPlotPhaseNoiseButton([bdroot'/PLL Testbench']);情节(xdpll码pll,'LineWidth'，2，'DisplayName','Digital PLL');