Deep Learning Processor IP Core

The generated deep learning (DL) processor IP core is a standard AXI interface IP core that contains:

To generate the DL processor IP core, use the HDL Coder™ IP core generation workflow. The generated IP core contains a standard set of registers and the generated IP core report. For more information, seeDeep Learning Processor Register Map.

The DL processor IP core reads inputs from the external memory and sends outputs to the external memory. The external memory buffer allocation is calculated by the compiler based on the network size and your hardware design. For more information, seeUse the Compiler Output for System Integration.

The input and output data stored in the external memory in a predefined format. For more information, seeExternal Memory Data Format.

Related Topics

• Custom IP Core Generation(HDL Coder)
• Use the Compiler Output for System Integration
• External Memory Data Format
• Deep Learning Processor Register Map
• Interface with the Deep Learning Processor IP Core