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Zynq and FMCOMMS2/3/4 Receiver Configuration

Connect hardware logic to FMCOMMSZynq无线电接收器硬件

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  • 库:

  • Xilinx设备的SOC阻万博1manbetx滞支持包/ SDR / AD9361

  • Zynq and FMCOMMS2/3/4 Receiver Configuration block

Description

TheZynq and FMCOMMS2/3/4 Receiver Configurationblock connects to the FMCOMMS2/3/4 radio receiver hardware in your hardware logic. In simulation, this block provides optional ports for center frequency and gain, which theSoC Buildertool maps to hardware pins. The block does not connect to the radio hardware from simulation.

Ports

输入

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External RF center frequency, specified as a nonnegative finite scalar on the port. The valid center frequency range is from 70 MHz to 6 GHz.

Dependencies

To enable this port, set theSource of center frequencyparameter to输入port.

Data Types:double

外增益，指定为数字标量。有效增益范围为–10 dB至77 dB。分辨率为0.25 dB。

Dependencies

To enable this port, set theSource of gainparameter to输入port.

Data Types:double

Parameters

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Source of center frequency, specified as one of these options:

  • Dialog— Set the center frequency by using theCenter frequency (Hz)parameter.

  • 输入port— Set the center frequency by using thecenter frequency输入端口。

RF center frequency, in Hz, specified as a nonnegative scalar. The valid range for center frequency is 70 MHz to 6 GHz.

Dependencies

To enable this parameter, set theSource of center frequencytoDialog.

Data Types:double

收益来源，指定为以下选项之一：

  • Dialog- 通过使用Gain (dB)parameter.

  • 输入port- 通过使用gain输入端口。

  • AGC Slow Attack–– Use this mode for signals with a slowly changing power level.

  • AGC Fast Attack–– Use this mode for signals with a rapidly changing power level.

Gain, in dB, specified as a numeric scalar. The valid gain range is -10 dB to 77 dB. The resolution is 0.25 dB.

Dependencies

To enable this parameter, setSource of gaintoDialog.

Data Types:double

Baseband sampling rate, in Hz, specified as a positive scalar. The valid range of this parameter is 520.834 kHz to 61.44 MHz.

Data Types:double

Advanced

When you select this parameter, the block applies in-phase and quadrature (IQ) imbalance compensation.

When you select this parameter, the block applies an RF direct current (DC) blocking filter.

当您选择此参数时，该块将应用一个基带DC阻止过滤器。

Model Examples

基于数据包的ADS-B收发器

基于数据包的ADS-B收发器

Packet-based systems are common in wireless communications. Data is received over the air and is decoded as discrete packet data on a compute device. For given system requirements, it is difficult to design a system and implement directly on SoC as it often involves long iterations of debugging and integration on hardware since hardware effects are difficult to account for at design time. In this example, you will design packet-based airplane tracking application based on Automatic Dependent Surveillance Broadcast (ADS-B) standard, partitioned between FPGA and embedded processor. Unlike traditional methods, you will simulate the application design with memory interface before implementation on hardware using SoC Blockset to shorten development time. You will then validate the design on hardware by automatically generated code from the model.

Extended Capabilities

版本历史

Introduced in R2019a

See Also