FPGA-in-the-Loop

Test designs in real hardware

在模拟器和董事会之间创建FPGA-IN-IN-IN-IN-IN-IN-IN链接链接，使您能够：

直接验证HDL实现Simulink中的算法万博1manbetx^®或matlab^®。
Apply data and test scenarios from Simulink or MATLAB to the HDL design on the FPGA.
将现有的HDL代码与Simulink或Matlab中正在开发的模型集成在一起。万博1manbetx

Before you can use FPGA-in-the-loop (FIL) simulation, you must download the support package for your board. SeeDownload FPGA Board Support Package。另外，您可以手动创建自定义板定义文件，以与FIL模拟一起使用。看FPGA Board Customization。

After you download a board support package, select a simulation workflow. SeeFPGA在环模拟中Workflows。要了解FIL模拟的工作原理，请参阅FPGA在环模拟中。

应用

FPGA在环向导

生成一个fpga-in-in-the-line-the-line块或系统对象从现有的HDL文件中

对象

hdlverifier.FILSimulation FIL simulation withMATLAB

功能

`filProgramFPGA`	将编程文件加载到FPGA
`programFPGA`	加载编程文件与`FILSimulation`系统对象到FPGA

块

FIL Simulation

从FPGA硬件上模拟HDL代码万博1manbetx

话题

概述

FPGA在环模拟中Workflows
Choose between generating a block or System object™, and decide whether to use the FIL Wizard or HDL Workflow Advisor.
FPGA在环模拟中
FPGA-in-the-loop (FIL) simulation provides the capability to use Simulink or MATLAB software for testing designs in real hardware for any existing HDL code.

FIL Requirements and Preparation

为FIL界面生成准备DUT
用于块和系统对象的FIL模拟的DUT指南。
Download FPGA Board Support Package
FPGA板支持软件包包含用于F万博1manbetxPGA-IN-IN-IN-IN-IN-IN-IN-IN-IN-IN-IN-THE-IN-THE-IN-THE-IN-THE-IN-THE-IN-TOBLE板的定义文件，FPGA数据捕获或AXI Manager。
Set Up FPGA Design Software Tools
将MATLAB路径设置为Xilinx^®，微膜^®, and Intel^®软件。
Guided Hardware Setup
Describes the steps in the automated support package setup process for configuring hardware for use with FPGA-in-the-loop.
手动硬件设置
Describes the steps necessary to prep hardware and hardware tools for FIL.

从旧代码生成FIL界面

通过FIL向导产生块
从现有的HDL源文件中生成FPGA-IN-IN-THE环块，然后在Simulink模拟中包含FPGA实现。万博1manbetx
System Object Generation with the FIL Wizard
从现有的HDL源文件中生成FPGA-IN-IN-in-the-liop系统对象，然后将FPGA实现包括在MATLAB模拟中。
使用FPGA-in-in-the-limop验证HDL实现PID控制器
此示例向您展示了如何使用HDL Verifier™设置FPGA-IN-IN-THE-IN-THE-THE-IOP（FIL）应用程序。
Verify Digital Up-Converter Using FPGA-in-the-Loop
此示例向您展示了如何使用FPGA-IN-IN-IN-IN-IN-IN-IN-IN-IN-IN-IN-IN-IN-INDL CODER™验证数字上连接设计。

Generate FIL System Object from MATLAB Code (requiresHDL编码器执照）

FIL Simulation with HDL Workflow Advisor for MATLAB
使用HDL Workflow Advisor生成FPGA-IN-IN-IN-IN-IN-IN-IN-IN-IN-IN-IN-IN-IN-IN-IN-IM系统对象和测试工作台。

从Simulink模型生成FIL块（需要万博1manbetxHDL编码器执照）

使用HDL Workflow Advisor生成测试工作台并启用代码覆盖（HDL编码器）
使用HDL Workflow Advisor生成测试工作台和代码覆盖范围。
与HDL Workflow顾问的FIL模拟万博1manbetx
Generate an FPGA-in-the-loop model using HDL Workflow Advisor.

故障排除

故障排除FIL

修复常见的错误消息和问题。

特色示例

使用MATLAB系统对象的FPGA在环上模拟

Uses a MATLAB® System object and an FPGA to verify a register transfer level (RTL) design of a Fast Fourier Transform (FFT) of size 8 written in Verilog. The FFT is commonly used in digital signal processing to produce frequency distribution of a signal.

开放示例

使用MATLAB系统对象和fpga-in-in-the-limop验证Viterbi解码器

使用MATLAB®系统对象和FPGA-IN-IN-IN-IN-IN-IN-IN-IN-IN-IN-IN-IN-the-limop模拟VITERBI解码器在FPGA上实现。

开放示例

使用FPGA-IN-IN-IN-IN-IN-IN-IN-IN-IN-THE CACLERATION

使用fpga-in-in-the-in-the-in-the-in-the-in-the-in-the-in-in-in-in-in-in-in-in-in-in-in-in-万博1manbetxin-in-in-in-in-n-nimulink®通过添加FPGA加速了视频处理模拟。所示的过程分析了一个简单的系统，该系统以每秒24帧的速度将RGB视频输入锐化。

开放示例

加速通信系统模拟使用FPGA-in-the-limop

使用FPGA-in-the-Loop (FIL)模拟accelerate part of a communications system. The application uses the Viterbi Algorithm to decode a convolutional encoded random stream that is BPSK modulated, sent through an AWGN channel, and then demodulated. Using a sample-by-sample approach leads to a modest speedup over normal Simulink® simulation, while using the "Process as Frames" option leads to further speedup.

Open Model

Algorithm Verification with a FIL Source Block

使用FPGA-IN-IN-THE-IOP（FIL）快速有效地验证HDL设计。测试台与正在测试的设计（DUT）合成，将结果下载到FPGA板，并使用FIL进行测试。使用FIL进行此过程，可以高速生成和测试刺激的处理，结果返回了Simulink进行分析。万博1manbetx此示例为图像处理用例执行这些任务。

开放示例