Phase-Locked Loops

Design and simulate analog phase-locked loop (PLL) systems

Design a PLL system starting from basic foundation blocks or from a family of reference architectures. Simulate and analyze the PLL system to verify key performance metrics until you meet the system specifications.

You can start by providing the specifications and impairments of each foundation block and connect the blocks to model different PLL architectural models (bottom-up approach). Alternatively, you can start from complete system-level models of typical PLL architectures and customize those models to meet your system specifications (top-down approach).

Use测量和试验台throughout the design process to verify the specifications of the blocks and of the entire system in presence of imperfections.

Blocks

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建筑模块

Charge Pump	输出与两个输入端口之间的占空比差异成比例的电流
Loop Filter	模型二阶，第三，或四阶无源环路滤波器
PFD	Phase/frequency detector that compares phase and frequency between two signals
VCO	Model voltage controlled oscillator
Ring Oscillator VCO	Model ring oscillator VCO
单个模数预分频器	Integer clock divider that divides frequency of input signal
Dual Modulus Prescaler	Integer clock divider with two divider ratios
分数时钟分频器与蓄能器	Clock divider that divides frequency of input signal by fractional number
Fractional Clock Divider with DSM	基于Delta Sigma调制器的分数时钟分频器

Reference Architectures

Fractional N PLL with Accumulator	Frequency synthesizer with accumulator based fractional N PLL architecture
Fractional N PLL with Delta Sigma Modulator	Frequency synthesizer with delta sigma modulator based fractional N PLL architecture
Integer N PLL with Dual Modulus Prescaler	Frequency synthesizer with dual modulus prescaler based integer N PLL architecture
Integer N PLL with Single Modulus Prescaler	Frequency synthesizer with single modulus prescaler based integer N PLL architecture

话题

Design and Evaluate Simple PLL Model
This example shows how to design a simple phase-locked loop (PLL) using a reference architecture and validate it using PLL Testbench.

Featured Examples

PLL Design and Verification Using Data Sheet Specifications

Use Mixed-Signal Blockset™ to model a commercial off-the-shelf integer-N phase-locked loop (PLL) with dual modulus prescaler operating around 4 GHz. You can verify the PLL performance, including phase noise.

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Phase Noise at PLL Output

Predict the phase noise at the output of a phase-locked loop (PLL), simulate the PLL using the PLL Testbench, and compare the simulation results to theoretical predictions.

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电路设计详细信息影响PLL性能

使用线性电路向导块评估环路滤波器电路设计细节对锁相环的性能的影响。

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Tune Phase-Locked Loop Using Loop-Shaping Design

调整被动环路滤波器的组件以改善锁相环（PLL）系统的环路带宽。为了获得所需的循环频率响应，该示例使用Control系统工具箱™软件中提供的固定结构调整方法计算环路滤波器参数。PLL系统使用来自混合信号块集™库的参考架构块进行建模。

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Digital Phase Locked Loop

模型一个数字phase locked loop using the Mixed-Signal Blockset™. In a digital phase locked loop, phase detection is performed by a time to digital converter (TDC), loop filtering is performed by a digital filter, and the oscillator is a digitally controlled oscillator (DCO). This example demonstrates a behavioral model of a TDC, using the BiquadFilter from the DSP Systen Toolbox™ as the digital loop filter, and using VCOs and DACs from the Mixed-Signal Blockset to model the DCO.

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