Simulink Design Verifier
万博1manbetx®Design Verifier™usesformal methodsto identify hidden design errors in models. It detects blocks in the model that result in integer overflow, dead logic, array access violations, and division by zero. It can formally verify that the design meets functional requirements. For each design error or requirements violation, it generates a simulation test case for debugging.
Simulink Design Verifiergenerates test cases for model coverage and custom objectives to extend existing requirements-based test cases. These test cases drive your model to satisfy condition, decision, modified condition/decision (MCDC), and custom coverage objectives. In addition to coverage objectives, you can specify custom test objectives to automatically generate requirements-based test cases.
Support for industry standards is available throughIEC Certification Kit(for IEC 61508 and ISO 26262) and做资格工具包(for DO-178).
Get Started
Learn the basics of Simulink Design Verifier
Systematic Model Verification
Identify and configure model components for analysis
Design Error Detection
Statically detect run-time errors and dead logic, derive design ranges
Test Case Generation
Generate systematic test cases from model, extend and combine test cases for full test suite
Requirements-Based Verification
Verify design against requirements, specify analysis input constraints
Complexity Management
Handle incompatibilities, optimize analysis for large and complex models
Results Interpretation and Use
Log and review analysis results, generate report, create test harness model
Verification and Validation
Use Simulink products to test models and code, check for design errors, check against standards, measure coverage, and validate the system
Tool Qualification and Certification
QualifySimulink Design Verifierfor IEC Certification