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Avnet RFSoC Explorer

versión 2.1.0 (114 MB) por Avnet
Connect to Xilinx UltraScale+™ RFSoC gigasample data converters. Perform analysis in MATLAB® and Simulink®. Deploy algorithms with HDL Coder
5.0
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Actualizada31 Jan 2022

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使用MATLAB和SIMULINK连接到Xilinx RFSOC万博1manbetx
AVNET RFSOCExplorer®提供了使用MATLAB和SIMULINK的Xilinx ZynxZynq®Ultrascale+™RFSOC的视觉接口。万博1manbetx直观的API可以对所有RF-ADC和RF-DAC参数，信号生成，采集进行编程控制。想要测试OTA信号的系统设计人员可以使用AVNET RFSOC Explorer来控制受欢迎的Xilinx RFSOC评估套件的支持的RF前端卡。万博1manbetx算法设计人员可以在RFSOC平台上生成IP内核。
Support and Documentation
RFSOC GEN-3的AVNET宽带MMWave无线电开发套件的入门指南
Getting started with HDL Coder for the Xilinx ZCU208 RFSoC Gen 3 development board
MathWorks RFSoC solutions page
Characterize RFSoC Performance
Development with Xilinx Zynq UltraScale+ RFSoC starts by characterizing the data converter subsystem using Avnet RFSoC Explorer. Avnet RFSoC Explorer enables you to use MATLAB and Simulink to stream standards-compliant 5G, LTE, and custom waveforms to and from hardware.
Avnet RFSoC Explorer System Diagram
Perform Over-the-Air Tests with RF Front-end Cards
Avnet RFSoC Explorer enables OTA testing by integrating control of RF front-ends connected to Xilinx Zynq UltraScale+ RFSoC Gen1 and Gen3 Evaluation Kits. Explore the entire signal chain in LTE 1800 MHz band-3 and mmWave bands between 19 and 31 GHz.
Supported platforms for RFSoC characterization and OTA test:
Deploy HDL Code for RFSoC
When you move into algorithm development, AVNET RFSOC资源管理器支持HDL万博1manbetx Coder™启用 可以使用XilinxVivado®设计套件将IP核心产生。
Avnet RFSoC Explorer HDL Coder Suppport for ZCU208
万博1manbetxHDL代码生成的支持平台：
使用此支持包，您可以万博1manbetx生成HDL代码和端口映射到I/O和AXI寄存器，以构建与RF图块和DDR内存的连接，并从MATLAB进行交互式控制FPGA设计。

Citar como

Avnet (2022).Avnet RFSoC Explorer(//www.tianjin-qmedu.com/matlabcentral/fileexchange/73665-avnet-rfsoc-explorer), MATLAB Central File Exchange. Recuperado.

compatibilidad conlaversióndematlab
SecreóConR2021b
Compatible con la versión R2021a a la R2021b
Compatibilidad con las plataformas
视窗 苹果系统 Linux

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