Design and Evaluate Simple PLL Model

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This example shows how to design a simple phase-locked loop (PLL) using a reference architecture and validate it using PLL Testbench.

A PLL is a frequency synthesizer system that produces an output signal whose phase depends on the phase of its input signal. In the simplest form, a PLL consists of a phase/frequency detector (PFD), charge pump, loop filter, voltage controlled oscillator (VCO), and a clock divider in a feedback loop. The PFD and charge pump together produce an error signal proportional to the phase difference of its two input signals. The loop filter removes the higher-frequency components of the error signal, which drives the VCO. The output of the VCO is fed through a clock divider to the input of the PFD, producing a negative feedback loop.

Mixed-Signal Blockset™ provides reference architectures to design a simple PLL model and testbenches to verify that the designed model meets the design specifications.

Set Up PLL Testbench Model

Open the modelsimplePLLattached to this example as a supporting file. The model consists of an Integer N PLL with Single Modulus Prescaler block and a PLL Testbench block.

open_system('simplePLL.slx')

PLL Specifications and Impairment

Use the data sheet ofSkyworks SKY73134-11to design the PLL system to lock at 2.8 GHz.

Double-click the Integer N PLL with Single Modulus Prescaler block to open the Block Parameters dialog box and verify these settings: * Check that the impairments are disabled in thePFDandCharge pumptabs. * In theCharge pumptab, theOutput currentis set to2.7mA. TheDeadband compensationandInput thresholdparameters are kept at default values.

In theVCOtab, theVCO Sensitivityis set to20MHz/V. TheFree running frequencyis slightly lower than the target lock frequency and is set to2.78GHz. ThePhase noise frequency offsetis set to[100e3 1e6 3e6 10e6]Hz and thePhase noise level (dBc/Hz)is set to[−108 −134 −145 −154]dBc/Hz.

Considering the reference input frequency to the PLL is1.6MHz, theClock divider valueand theMin clock divider valuein thePrescalertab is set to $$\frac{2\ldotp 8\textrm{e9}}{1\ldotp 6\textrm{e6}}=1750$ .

In theLoop Filtertab, theLoop bandwidthis set to160kHz, 1/10th of the reference input frequency. The phase margin is kept at default 45 degrees.Filter component valuesare calculated automatically.

In theAnalysistab, bothOpen Loop AnalysisandClosed Loop Analysisplots are selected.

Plot Presimulation PLL Loop Dynamics

Click thePlot Loop Dynamicsbutton to view the presimulation results and aseess the stability of the system.

The closed loop analysis consists of the Pole-Zero Map, Magnitude Response, Step Response, and Impulse Response. The 3-dB bandwidth of the system is288.51kHz. The system is stable.

The open loop analysis consists of Bode plots of the PLL system. The phase margin is44.1degrees and the unity gain frequency is159.9kHz.

Modify PLL Testbench for Phase Noise Measurement

Double-click the PLL Testbench to open the Block Parameters dialog box and verify these settings: * In theStimulustab, the input signal to the PLL is defined as a square wave of1.6MHz.

In theSetuptab, check that thePhase noisemeasurement option is selected.Frequency of operationandLock timemeasurement options are deselected. Set theResolution bandwidthto50kHz,No. of spectral averagesto4and推迟时间to1.5e-5s.

In theTarget Metricstab, set thePhase noise (dBc/Hz)to[−108 −134 −145 −154], the same as the PLL phase noise profile.

Plot PLL Phase Noise Profile

Run the simulation for1.35e-4s. The simulation results are displayed on the icon of the PLL Testbench. The measured phase noise levels at specific frequency offsets are consistent with their target values.

Double-click the PLL Testbench block to open the Block Parameters dialog box. Click thePlot phase noise profilebutton. The PLL operating frequency is2.8GHz, and the measured phase noise profile matches the target profile.

Reference

1.Skyworks SKY73134-11