内存

Design and develop the shared memory and data register components of an SoC application

SoC Blockset™ enables simulation and evaluation of shared memory transactions in Simulink^®. To include a memory system in your SoC model, configure a memory controller for the desired number of memory channels, and then connect the controller to memory channel blocks for arbitrating and handling memory traffic.

SoC Blockset enables the simulation and evaluation of shared memory transactions in Simulink. Visualize post-simulation performance and bandwidth metrics before deploying to SoC device by using theLogic Analyzer应用程序。

Blocks

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内存Model

内存Channel	Stream data through a memory channel
内存Controller	Arbitrate memory transactions for one or more Memory Channel blocks
内存Traffic Generator	Generate traffic towards memory controller
Register Channel	Timing model for transfer of register values
Interrupt Channel	Send interrupt to processor from hardware
AXI4 Master Sink	Receive random access memory data
AXI4 Master Source	Generate random access memory data
Stream Data Sink	Receive continuous stream data
Stream Data Source	Generate continuous stream data

Hardware Logic Connectivity

SoC Bus Selector	Convert bus to control signals
SoC Bus Creator	Convert control signals to bus
Stream FIFO	Control backpressure between hardware logic and upstream data interface
Stream Connector	Connect two IPs with data streaming interfaces
IP Core Register Read	Model register writes from software to hardware

Processor Software Connectivity

Register Read	Read data from a register region on the specified IP core
Register Write	Write data to a register region on the specified IP core
Stream Read	Stream data from shared memory to processor algorithms
Stream Write	Stream data from processor algorithms to shared memory

Video Stream Connectivity

Video Stream FIFO	Control backpressure between hardware logic and upstream video interface
Video Stream Connector	Connect two IPs with video streaming interfaces

Apps

Logic Analyzer

Visualize, measure, and analyze transitions and states over time

Tools

内存Mapper

Configure memory map for SoC application

Model Settings

Hardware Implementation Pane

Topics

Design

内存and Register Data Transfers
Introduction to memory and register transfers.
External Memory Channel Protocols
Supported memory channel protocols and control signals.
AXI4-Stream Interface
How to design your model for AXI4-Stream vector or scalar interface generation.
Simplified AXI4 Master Interface
Description of AXI4 Master protocol, and how you can design your model for IP core generation with AXI4-Master interfaces.
AXI4-Stream Video Interface
How to design your model for IP core generation with AXI4-stream video interfaces.

Simulation

Simulation Diagnostics
SoC Blockset enables simulation and evaluation of memory transactions in Simulink without the need to deploy a model to an SoC device.
Simulation Performance Tips
Suggestions for enhancing simulation performance of SoC models.
Simulation Performance Plots
SoC Blockset enables post-simulation analysis of memory diagnostic data.

Measurement

内存Performance Information from FPGA Execution
Obtain memory interconnect traffic information from a design running on FPGA.

Featured Examples

Random Access of External Memory

从FPGA为rotat模型外部存储器访问ing an ASCII art image. Many applications require FPGA to access memory in random fashion as per the requirements of algorithm. You will learn how to design memory address generation along with other AXI4 master signals to read and write specific regions of memory using SoC Blockset. You will simulate, implement and verify your design on hardware.

Open Example

Histogram Equalization Using Video Frame Buffer

Video processing applications often store a full frame of video data to process the frame and modify the next frame. In such designs video frames are stored in external memory while FPGA resources are used to process same data. This example shows how to design a video application with HDMI input and output performing histogram equalization using external memory for video frame buffering.

Open Example

Triggering Software Tasks by FPGA Interrupts

Model an algorithm partitioned between hardware and software. The hardware IP is implemented in FPGA fabric, and triggers a software task implemented in the embedded processor. Design, simulate, and implement a complete design on SoC hardware.

Open Example

Vertical Video Flipping Using External Memory

Design an application to flip an incoming video stream vertically. You will use external memory to store a video frame to accomplish this task. You can use this technique for designing and implementing other vision applications requiring access to the external memory.

Contrast Limited Adaptive Histogram Equalization with External Memory

Implement the contrast-limited adaptive histogram equalization (CLAHE) algorithm for FPGA, including an external memory interface.

Open Model

Accelerate SoC Simulation by Varying Abstraction Levels

Different levels of abstraction available for SoC architecture and how to accelerate the simulation speed of SoC models by choosing the right abstraction level.

Open Live Script

Analyze Memory Bandwidth Using Traffic Generators

Demonstrates how to analyze memory bandwidth for an SoC application. In memory-intensive hardware designs, you may have multiple masters accessing a common DDR memory. In such cases, it is important to analyze the dynamic requirement of all memory masters to guide algorithm design and hardware board requirement for deployment. You can simulate the memory traffic using Memory traffic generators, analyze the bandwidth usage and verify it on the hardware.

Open Example

Receive Signal Waveform Using DDR4 on Xilinx RFSoC Device

Design, simulate, and deploy a system to write and read the captured RF samples from external double data rate 4 (DDR4) memory in Simulink® with an SoC Blockset® implementation targeted on the Xilinx® Zynq® UltraScale+™ RFSoC ZCU111 evaluation kit. In this example, you can write the captured samples of an analog-to-digital converter (ADC) into external programmable logic (PL) DDR4 memory, read the samples from the PL DDR4 memory, and send them to the processor to display. A tone signal is generated in FPGA using a numerically controlled oscillator (NCO) to verify the receive path.

Open Example