主要内容

SDR Template

软件定义的无线电（SDR）模板为可从可用的SOC参考设计提供了模拟模型Communications Toolbox™ Support Package for Xilinx®Zynq®-Based Radio。Use this template to simulate the full reference design and analyze the effects of internal and external connectivity on and SDR algorithm, such as memory behavior and Radio Frequency (RF) I/O behavior.

To get started with SoC Blockset™ model for designing an SDR system, follow the steps toCreate SoC Model Using SoC Blockset Template。

Required Products

  • Communications Toolbox

  • Xilinx设备的SOC阻万博1manbetx滞支持包

Template Structure

This template models an SDR transceiver composed of AD9361 transmitter and receiver blocks. The transceiver connects an RF channel to the FPGA, which implements a receiver and a transmitter algorithm. The FPGA algorithm includes aTest Sourceblock, which generates a sinusoid signal and drives it to the transmitter. The FPGA algorithm also includes a Tx algorithm, implemented as simple pass-through wires, and an Rx algorithm, implemented as a gain block. A configuration registersrcselis modeled in the FPGA to select the source of data for the Rx algorithm. The processor writes thesrcselregister to select either the test source from the FPGA or RF data from the transceiver. This register is modeled using theRegister Channel堵塞。FPGA算法的数据通过A传递给处理器内存频道堵塞。

Use this template as a guide and replace the Rx Algorithm and Tx Algorithm in the FPGA and the Processor Algorithm in the processor with your own functionality. The memoryChannel Type参数设置为通过DMA到软件的Axi4-stream，通过共享外部内存进行建模直接内存访问（DMA）数据传输。

处理器从内存中读取计算的数据，并执行其他计算（在模板中以传递电线为单位）。您可以通过双击来查看仿真结果Vector Scope块中的测试台水槽。

修改项目

Modify the FPGA Model

在Matlab®, on theProject Shortcutstab, clickOpen FPGA sample model。这n, open the FPGA Tx-Rx Alg Wrapper. Notice three areas highlighted in green. These areas represent user code and are located in the Receiver Algorithm block, in the Transmitter Algorithm block, and the Test Source block.

FPGA模型包括以下各节供您修改（以绿色突出显示）：

  • Test Source block – This block generates a 10-kHz sinusoid signal and drives it to the transmitter algorithm. Modify the test source to your needs or replace it with an alternative source block.

  • Receiver Algorithm subsystem – Inside the green-highlighted subsystem namedRx Algorithm, there is a block labeled Algorithm. The algorithm takes I/Q data as input and output with a valid signal. Replace this block with your own Rx algorithm.

  • 发射机算法 - 命名的绿色高光子系统Tx Algorithm，该算法具有来自测试源的输入和两个输出信号：一个到RF通道，一个到FPGA。用自己的TX算法替换此块。

To enable consistent simulation behavior, in theProject Shortcutstab, clickOpen FPGA frame modeland repeat this step.

Modify the Processor Model

在Matlab，在Project Shortcutstab, clickOpen processor model。蓝色突出显示的子系统表示处理器算法的用户代码。打开处理器算法包装器并更换内部Processor Algorithm带有所需算法的块（也以蓝色突出显示）。

Modify the Register Channel

模板的顶部模型还包括一个寄存器通道，以在处理器和FPGA模型之间进行通信。使用寄存器频道配置FPGA模型或读取和检查状态寄存器。这Register Channelblock in the template includes one register. To add additional registers you must modify the register channel block parameters, the FPGA algorithm, and the processor algorithm:

  1. 将寄存器添加到寄存器频道 - 双击Register Channelblock to open the block mask and add additional registers as needed. Adding registers creates additional ports on theRegister Channel堵塞。For additional information, seeRegister Channel。

  2. 将端口添加到处理器模型 - 导航到Processor Algorithm Wrapper模型。要导航到处理器模型，请单击Open Processor modelon theProject Shortcuts标签。双击Processor Algorithm Wrapperto modify it.

    For write registers, add an output port to the module and add logic to drive a value to the added output port. For read registers, add an input port and logic to process the information returned from a read register. From the top model, wire the port to theRegister Channel堵塞。

  3. Add ports to the FPGA model – Navigate to theFPGA Algorithm Wrapper模型。要导航到基于FPGA/框架的处理模型，请单击Open FPGA sample modelon theProject Shortcuts标签。双击FPGA Algorithm Wrapperto modify it.

    为写寄存器,modu添加一个输入端口le and logic to process the information returned from a read register. For read registers, add an output port and logic to drive a value to the added output port.

    使用Simulink时的等效行为万博1manbetx®基于样本的变体，在FPGA包装器中重复此步骤，以获取基于样本的处理模型。

  4. 从顶部模型，将新端口连接到Register Channel堵塞。