Hardware Support

Microsemi FPGA Board Support from HDL Verifier

Debug and test HDL code on Microsemi FPGAs using FPGA-in-the-loop

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      Capabilities and Features

      HDL Verifier™ automates the verification of HDL code on Microsemi®FPGA boards by enabling FPGA-in-the-loop (FIL) simulation. FIL simulation helps ensure that the MATLAB®algorithm or Simulink®design behaves as expected in the real world, increasing confidence in your silicon implementation.

      The MATLAB algorithm or Simulink model is used to drive FPGA input stimuli and to analyze the output of the FPGA.

      With FIL testing, you can verify your design at FPGA speeds, enabling you to run more extensive sets of test cases and perform regression tests on your design.

      When used with HDL Coder, you can use HDL Workflow Advisor to generate the FIL model for Simulink and generate the FPGA programming file for the Microsemi FPGA.

      HDL Verifier supports FIL simulation for the following Microsemi FPGA boards:

      SeeMicrosemi Usage Requirementsfor information about supported versions of Microsemi Libero®SoC software.

      HDL Verifier provides FPGA-in-the-Loop verification on Microsemi PolarFire, RTG4, and SmartFusion2 development kits.

      Platform and Release Support

      See thehardware support package system requirements tablefor current and prior version, release, and platform availability.

      View enhancements and bug fixes inrelease notes.

      Related Resources

      Required Products and Hardware

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