HDL Block Properties: General

Overview

Block implementation parameters enable you to control details of the code generated for specific block implementations. SeeSet and View HDL Model and Block Parametersto learn how to select block implementations and parameters in the GUI or the command line.

Property names are specified as character vectors. The data type of a property value is specific to the property. This section describes the syntax of each block implementation parameter and how the parameter affects generated code.

HDL Block Properties of Library Blocks

HDL block properties of library blocks are treated similar to mask parameters. When you instantiate library blocks in your model, the current HDL block properties of that library block are copied to instances of that block in your model. The HDL block properties of these instances are not synchronized with the HDL block properties of the library block. That is, if you change the HDL block property of the library block, the change does not get propagated to instances of the library block that you already added to your Simulink^®model. If you want the HDL block properties of a library block to be synchronized with its instances in the model, create aSubsystemand then place this block inside thatSubsystem. The HDL block properties of blocks that reside inside the library block are synchronized with the corresponding instances in your model.

Suppose a library contains aSubsystemblock with HDL architecture set toModule. When you instantiate this block in your model, the block instance usesModuleas the HDL architecture. If you change the HDL architecture of theSubsystemblock in the library toBlackBox, existing instances of thatSubsystemblock in your model still useModuleas the HDL architecture. If you now add instances of theSubsystemblock from the library in your model, the new block instances get a copy of the current HDL block properties, and therefore useBlackBoxas the HDL architecture. If you want the HDL architecture of theSubsystemblock in the library to be synchronized with its instances in the model, create a wrapper subsystem with the HDL architecture that you want inside thisSubsystem.

AdaptivePipelining

TheAdaptivePipeliningsubsystem parameter enables you to set adaptive pipelining on a subsystem within a model.

Adaptive Pipelining Setting	Description
`'inherit'`(default)	Use the adaptive pipelining setting of the parent subsystem. If this subsystem is the highest-level subsystem, use the adaptive pipelining setting for the model.
`'on'`	Insert adaptive pipelines for this subsystem.
`'off'`	Do not insert adaptive pipelines for this subsystem, even if the parent subsystem has adaptive pipelining enabled.

To disable adaptive pipelining for a subsystem within a model, set the adaptive pipelining parameter,AdaptivePipelining, to'off'for that subsystem.

To learn how to set model-level adaptive pipelining, seeAdaptive pipelining.

Set Adaptive Pipelining For a Subsystem

To set adaptive pipelining for a subsystem from the HDL Block Properties dialog box:

Right-click the subsystem and selectHDL Code>HDL Block Properties.
ForAdaptivePipelining, selectinherit,on, oroff.

To set adaptive pipelining for a subsystem from the command line, usehdlset_param. For example, to turn off adaptive pipelining for a subsystem,my_dut:

hdlset_param(“我的_dut','AdaptivePipelining','off')

See alsohdlset_param.

BalanceDelays

TheBalanceDelayssubsystem parameter enables you to set delay balancing on a subsystem within a model.

BalanceDelays Setting	Description
`'inherit'`(default)	Use the delay balancing setting of the parent subsystem. If this subsystem is the highest-level subsystem, use the delay balancing setting for the model.
`'on'`	Balance delays for this subsystem.
`'off'`	Do not balance delays for this subsystem, even if the parent subsystem has delay balancing enabled.

To disable delay balancing for any subsystem within a model, you must set the model-level delay balancing parameter,BalanceDelays, to'off'. When delay balancing is enabled on the model, the delay balancing setting on individual subsystems is ignored.

To learn how to set model-level delay balancing, seeBalance delays.

Set Delay Balancing For a Subsystem

To set delay balancing for a subsystem using the HDL Block Properties dialog box:

Right-click the subsystem.
SelectHDL Code>HDL Block Properties.
ForBalanceDelays, selectinherit,on, oroff.

To set delay balancing for a subsystem from the command line, usehdlset_param. For example, to turn off delay balancing for a subsystem,my_dut:

hdlset_param(“我的_dut','BalanceDelays','off')

See alsohdlset_param.

ClockRatePipelining

TheClockRatePipeliningsubsystem parameter enables you to set clock-rate pipelining on a subsystem within a model.

Clock-Rate Pipelining Setting	Description
`'inherit'`(default)	Use the clock-rate pipelining setting of the parent subsystem. If this subsystem is the highest-level subsystem, use the clock-rate pipelining setting for the model.
`'on'`	Insert clock-rate pipelines for this subsystem.
`'off'`	Do not insert clock-rate pipelines for this subsystem, even if the parent subsystem has clock-rate pipelining enabled.

To disable clock-rate pipelining for a subsystem within a model, set the clock-rate pipelining parameter,ClockRatePipelining, to'off'for that subsystem.

To learn how to set model-level clock-rate pipelining, seeClock-rate pipelining.

Set Clock-Rate Pipelining For a Subsystem

To set clock-rate pipelining for a subsystem using the HDL Block Properties dialog box:

Right-click the subsystem.
SelectHDL Code>HDL Block Properties.
ForClockRatePipelining, selectinherit,on, oroff.

To set clock-rate pipelining for a subsystem from the command line, usehdlset_param. For example, to turn off clock-rate pipelining for a subsystem,my_dut:

hdlset_param(“我的_dut','ClockRatePipelining','off')

See alsohdlset_param.

CodingStyle

When you useMultiport Switchblocks, use theCodingStyleparameter to specify whether you want to generate HDL code with if-else or case statements. By default, HDL Coder™ generates if-else statements. If you have severalMultiport Switchblocks in your model, you can choose to specify a differentCodingStylefor each block.

CodingStyle设置	Description
`'ifelse_stmt'`(Default)	Generate if-else statements in the Verilog code or when-else statements in the VHDL code for aMultiport Switchblock.
`'case_stmt'`	Generate case statements in the Verilog code or case-when statements in the VHDL code for aMultiport Switchblock.

Set CodingStyle ForMultiport SwitchBlock

To set CodingStyle for aMultiport Switchusing the HDL Block Properties dialog box:

Right-click theMultiport Switchblock.
SelectHDL Code>HDL Block Properties.
ForCodingStyle, selectifelse_stmtorcase_stmt.

To see theCodingStylespecified for a subsystem from the command line, usehdlget_param. For example, to see the settings specified for aMultiport Switchblock inside a subsystem,my_dut:

hdlget_param(“我的_dut/Multiport Switch','CodingStyle')

ans = 'case_stmt'

See alsohdlset_param.

ConstMultiplierOptimization

TheConstMultiplierOptimizationimplementation parameter lets you specify use of canonical signed digit (CSD) or factored CSD optimizations for processing coefficient multiplier operations in the generated code.

The following table shows theConstMultiplierOptimizationparameter values.

ConstMultiplierOptimization Setting	Description
`'none'` (Default)	By default, HDL Coder does not perform CSD or FCSD optimizations. Code generated for the Gain block retains multiplier operations.
`'CSD'`	When you specify this option, the generated code decreases the area used by the model while maintaining or increasing clock speed, using canonical signed digit (CSD) techniques. CSD replaces multiplier operations with add and subtract operations. CSD minimizes the number of addition operations required for constant multiplication by representing binary numbers with a minimum count of nonzero digits.
`'FCSD'`	This option uses factored CSD (FCSD) techniques, which replace multiplier operations with shift and add/subtract operations on certain factors of the operands. These factors are generally prime but can also be a number close to a power of 2, which favors area reduction. This option lets you achieve a greater area reduction than CSD, at the cost of decreasing clock speed.
`'auto'`	当你指定这个选项,高密度脂蛋白编码器选择tween the CSD or FCSD optimizations. The coder chooses the optimization that yields the most area-efficient implementation, based on the number of adders required. When you specify`'auto'`, the coder does not use multipliers, unless conditions are such that CSD or FCSD optimizations are not possible (for example, if the design uses floating-point arithmetic).

TheConstMultiplierOptimizationparameter is available for the following blocks:

Gain
Stateflow^®chart
Truth Table
MATLAB Function
MATLAB System

ConstrainedOutputPipeline

Use theConstrainedOutputPipelineparameter to specify a nonnegative number of registers to place at the block outputs.

HDL Coder moves existing delays within your design to try to meet your constraint. New registers are not added. If there are fewer registers than the coder needs to satisfy your constraint, the coder reports the difference between the number of desired and actual output registers. You can add delays to your design using input or output pipelining.

Distributed pipelining does not redistribute registers you specify with constrained output pipelining.

How to Specify Constrained Output Pipelining

To specify constrained output pipelining for a block using the GUI:

Right-click the block and selectHDL Code>HDL Block Properties.
ForConstrainedOutputPipeline, enter the number of registers you want at the output ports.

To specify constrained output pipelining, at the command line, enter:

hdlset_param(path_to_block,'ConstrainedOutputPipeline', number_of_output_registers)

For example, to constrain 6 registers at the output ports of a subsystem,subsys, in your model,mymodel, enter:

hdlset_param(“我的model/subsys','ConstrainedOutputPipeline', 6)

DistributedPipelining

TheDistributedPipelining参数使流水线寄存器分配,a speed optimization that enables you to increase your clock speed by reducing your critical path.

The following table shows the effect of theDistributedPipeliningandOutputPipelineparameters.

DistributedPipelining	OutputPipeline, nStages	Result
`'off'`(default)	Unspecified (`nStages`defaults to 0)	HDL Coder does not insert pipeline registers.
`'off'`(default)	`nStages`> 0	The coder inserts`nStages`output registers at the output of the subsystem,MATLAB Functionblock, or Stateflow chart.
`'on'`	Unspecified (`nStages`defaults to 0)	The coder does not insert pipeline registers. `DistributedPipelining`has no effect.
`'on'`	`nStages`> 0	The coder distributes`nStages`registers inside the subsystem,MATLAB Functionblock, or Stateflow chart, based on critical path analysis.

To achieve further optimization of code generated with distributed pipelining, perform retiming during RTL synthesis, if possible.

Tip

Output data might be in an invalid state initially if you insert pipeline registers. To avoid test bench errors resulting from initial invalid samples, disable output checking for those samples. For more information, seeIgnore output data checking (number of samples).

DotProductStrategy

If you use theProductblock for matrix multiplication in your design, use theDotProductStrategyto specify how you want to implement the matrix multiplication.

TheDotProductStrategyoptions are listed in the following table.

DotProductStrategy Value Description

DotProductStrategy Value	Description
`'Fully Parallel'`(default)	Expands the matrix multiplication operation into multipliers and adders. For example, if you multiply two 2x2 matrices, the implementation uses eight multipliers and four adders to compute the result. Note TheDotProductStrategymust be set to`'Fully Parallel'`when you use the`Native Floating Point`mode.
`'Serial Multiply-Accumulate'`	Uses theSerialarchitecture of theMultiply-Accumulateblock to implement the matrix multiplication. In this architecture, the clock rate must be faster than the clock rate that you specify withParallelarchitecture. You can see the clock rate in the Clock Summary information of the Code Generation report.
`'Parallel Multiply-Accumulate'`	Uses theParallelarchitecture of theMultiply-Accumulateblock to implement the matrix multiplication.

'Fully Parallel'(default)

Expands the matrix multiplication operation into multipliers and adders. For example, if you multiply two 2x2 matrices, the implementation uses eight multipliers and four adders to compute the result.

Note

TheDotProductStrategymust be set to'Fully Parallel'when you use theNative Floating Pointmode.

'Serial Multiply-Accumulate'

Uses theSerialarchitecture of theMultiply-Accumulateblock to implement the matrix multiplication.

In this architecture, the clock rate must be faster than the clock rate that you specify withParallelarchitecture. You can see the clock rate in the Clock Summary information of the Code Generation report.

'Parallel Multiply-Accumulate'

Uses theParallelarchitecture of theMultiply-Accumulateblock to implement the matrix multiplication.

DSPStyle

DSPStyle允许您生成代码,包括辛迪思is attributes for multiplier mapping in your design. You can choose whether to map a particular block’s multipliers to DSPs or logic in hardware.

For Xilinx^®targets, the generated code uses theuse_dspattribute. For Altera^®targets, the generated code uses themultstyleattribute.

TheDSPStyleoptions are listed in the following table.

DSPStyle Value	Description
`'none'`(default)	Do not insert a DSP mapping synthesis attribute.
`'on'`	Insert synthesis attribute that directs the synthesis tool to map to DSPs in hardware.
`'off'`	Insert synthesis attribute that directs the synthesis tool to map to logic in hardware.

TheDSPStyleparameter is available for the following blocks:

Gain
Product
Product of Elementswith Architecture set to Tree
Subsystem
Atomic Subsystem
Variant Subsystem
Enabled Subsystem
Triggered Subsystem
Modelwith Architecture set toModelReference

Hierarchy Flattening Behavior

If you specify hierarchy flattening for a subsystem that also has a nondefaultDSPStylesetting, HDL Coder propagates theDSPStylesetting to the parent subsystem.

If the flattened subsystem containsGain,Product, orProduct of Elementsblocks, the coder keeps their nondefaultDSPStylesettings, and replaces defaultDSPStylesettings with the flattened subsystemDSPStylesetting.

Synthesis Attributes in Generated Code

The generated code for synthesis attributes depends on:

Target language
DSPStylevalue
SynthesisToolvalue

The following table shows examples of synthesis attributes in generated code.

DSPStyle Value	TargetLanguage Value	SynthesisTool Value
DSPStyle Value	TargetLanguage Value	`'Altera Quartus II'`	`'Xilinx ISE'` `'Xilinx Vivado'`
`'none'`	`'Verilog'`	`wire signed [32:0] m4_out1;`	`wire signed [32:0] m4_out1;`
`'none'`	`'VHDL'`	`m4_out1 : signal;`	`m4_out1 : signal;`
`'on'`	`'Verilog'`	`(* multstyle = "dsp" *) wire signed [32:0] m4_out1;`	`(* use_dsp = "yes" *) wire signed [32:0] m4_out1;`
`'on'`	`'VHDL'`	`attribute multstyle : string ;` `attribute multstyle of m4_out1 : signal is "dsp" ;`	`attribute use_dsp : string ;` `attribute use_dsp of m4_out1 : signal is "yes" ;`
`'off'`	`'Verilog'`	`(* multstyle = "logic" *) wire signed [32:0] m4_out1;`	`(* use_dsp = "no" *) wire signed [32:0] m4_out1;`
`'off'`	`'VHDL'`	`attribute multstyle : string ;` `attribute multstyle of m4_out1 : signal is "logic" ;`	`attribute use_dsp : string ;` `attribute use_dsp of m4_out1 : signal is "no" ;`

Requirement For Synthesis Attribute Specification

You must specify a synthesis tool by using theSynthesisToolproperty.

How To Specify a Synthesis Attribute

To specify a synthesis attribute using the HDL Block Properties dialog box:

Right-click the block.
SelectHDL Code>HDL Block Properties.
ForDSPStyle, selecton,off, ornone.

To specify a synthesis attribute from the command line, usehdlset_param. For example, suppose you have a model,my_model, with a DUT subsystem,my_dut, that contains a . Gain block,my_multiplier. To insert a synthesis attribute to mapmy_multiplierto a DSP, enter:

hdlset_param(“我的_model/my_dut/my_multiplier','DSPStyle','on')

See alsohdlset_param.

Limitations For Synthesis Attribute Specification

When you specify a nondefaultDSPStyleblock property, theConstMultiplierOptimizationproperty must be set to'none'.
Inputs to multiplier components cannot use thedoubledata type.
Gainconstant cannot be a power of 2.

FlattenHierarchy

FlattenHierarchyenables you to remove subsystem hierarchy from the HDL code generated from your design.

FlattenHierarchy Setting	Description
`'inherit'`(default)	Use the hierarchy flattening setting of the parent subsystem. If this subsystem is the highest-level subsystem, do not flatten.
`'on'`	Flatten this subsystem.
`'off'`	Do not flatten this subsystem, even if the parent subsystem is flattened.

To flatten hierarchy, you must also have theMaskParameterAsGenericglobal property set to'off'. For more information, seeGenerate parameterized HDL code from masked subsystem.

How To Flatten Hierarchy

To set hierarchy flattening using the HDL Block Properties dialog box:

In theAppstab, selectHDL Coder. TheHDL Codetab appears. Select theSubsystemand then clickHDL Block Properties. ForFlattenHierarchy, selecton,off, orinherit.
Right-click theSubsystemand selectHDL Code>HDL Block Properties. ForFlattenHierarchy, selecton,off, orinherit.

To set hierarchy flattening from the command line, usehdlset_param. For example, to turn on hierarchy flattening for a subsystem,my_dut:

hdlset_param(“我的_dut','FlattenHierarchy','on')

See alsohdlset_param.

Limitations For Hierarchy Flattening

A subsystem cannot be flattened if the subsystem is:

ASynchronous Subsystemor uses theState Controlblock inSynchronousmode.
A model reference implementation.
A Triggered Subsystem whenUse trigger signal as clockis enabled.
A masked subsystem that contains any of the following:
- Bus.
- Enumerated data type.
- Lookup table blocks:1-D Lookup Table,2-D Lookup Table,Cosine HDL Optimized,Direct LookupTable (n-D),Prelookup,Sine HDL Optimized,n-D Lookup Table.
- MATLAB Systemblock.
- Stateflow blocks:Chart,State Transition Table,Sequence Viewer.
- Blocks with a pass-through or no-op implementation. SeePass through, No HDL, and Cascade Implementations.

Note

This option removes subsystem boundaries before code generation. It does not necessarily generate HDL code with a completely flat hierarchy.

InputPipeline

InputPipelinelets you specify a implementation with input pipelining for selected blocks. The parameter value specifies the number of input pipeline stages (pipeline depth) in the generated code.

The following code specifies an input pipeline depth of two stages for each Sum block in the model:

sblocks = find_system(gcb, 'BlockType', 'Sum'); for ii=1:length(sblocks),hdlset_param(sblocks{ii},'InputPipeline', 2), end;

Note

TheInputPipelinesetting does not have any effect on blocks that do not have an input port.

When generating code for pipeline registers, HDL Coder appends a postfix string to names of input or output pipeline registers. The default postfix string is_pipe. To customize the postfix string, use thePipeline postfixoption in theGlobal Settings / Generalpane in theHDL Code Generationpane of the Configuration Parameters dialog box. Alternatively, you can pass the desired postfix as a character vector in themakehdlpropertyPipelinePostfix. For an example, seePipeline postfix.

InstantiateFunctions

For the MATLAB Function block, you can use theInstantiateFunctionsparameter to generate a VHDL^®entityor Verilog^®modulefor each function. HDL Coder generates code for eachentityormodulein a separate file.

TheInstantiateFunctionsoptions for theMATLAB Functionblock are listed in the following table.

InstantiateFunctions Setting	Description
`'off'`(default)	Generate code for functions inline.
`'on'`	Generate a VHDL`entity`or Verilog`module`for each function, and save each`module`or`entity`in a separate file.

How To Generate Instantiable Code for Functions

To set theInstantiateFunctionsparameter using the HDL Block Properties dialog box:

Right-click theMATLAB Functionblock.
SelectHDL Code>HDL Block Properties.
ForInstantiateFunctions, selecton.

To set theInstantiateFunctionsparameter from the command line, usehdlset_param. For example, to generate instantiable code for functions in aMATLAB Functionblock,myMatlabFcn, in your DUT subsystem,myDUT, enter:

hdlset_param('my_DUT/my_MATLABFcnBlk', 'InstantiateFunctions', 'on')

Generate Code Inline for Specific Functions

If you want to generate instantiable code for some functions but not others, enable the option to generate instantiable code for functions, and usecoder.inline. Seecoder.inlinefor details.

限制Instantiable Code Generation for Functions

The software generates code inline when:

Function calls are within conditional code orforloops.
Any function is called with a nonconstantstructinput.
The function has state, such as a persistent variable, and is called multiple times.
There is an enumeration anywhere in the design function.

InstantiateStages

For aCascadearchitecture, you can use theInstantiateStagesparameter to generate a VHDLentityor Verilogmodulefor each computation stage. HDL Coder generates code for eachentityormodulein a separate file.

InstantiateStages Setting	Description
`'off'`(default)	Generate cascade stages in a single VHDL`entity`or Verilog`module`.
`'on'`	Generate a VHDL`entity`or Verilog`module`for each cascade stage, and save each`module`or`entity`in a separate file.

LoopOptimization

LoopOptimizationenables you to stream or unroll loops in code generated from aMATLAB Functionblock. Loop streaming optimizes for area; loop unrolling optimizes for speed.

Note

If you specify theMATLAB Datapatharchitecture of theMATLAB Functionblock, you can only unroll loops. To stream loops, you can use the streaming optimization by specifying aStreamingFactor. SeeHDL Optimizations Across MATLAB Function Block Boundary Using MATLAB Datapath Architecture.

LoopOptimization Setting	Description
`'none'`(default)	Do not optimize loops.
`'Unrolling'`	Unroll loops.
`'Streaming'`	Stream loops.

How to OptimizeMATLAB FunctionBlock For Loops

To select a loop optimization using the HDL Block Properties dialog box:

Right-click theMATLAB Functionblock.
SelectHDL Code>HDL Block Properties.
ForLoopOptimization, selectnone,Unrolling, orStreaming.

To select a loop optimization from the command line, usehdlset_param. For example, to turn on loop streaming for aMATLAB Functionblock,my_mlfn:

hdlset_param(“我的_mlfn','LoopOptimization','Streaming')

See alsohdlset_param.

限制MATLAB FunctionBlock Loop Optimization

HDL Coder cannot stream a loop if:

The loop index counts down. The loop index must increase by 1 on each iteration.
There are 2 or more nested loops at the same level of hierarchy within another loop.
Any particular persistent variable is updated both inside and outside a loop.

HDL Coder can stream a loop when the persistent variable is:

Updated inside the loop and read outside the loop.
Read within the loop and updated outside the loop.

LUTRegisterResetType

Use theLUTRegisterResetTypeblock parameter to control synthesis of a LUT into a ROM structure on an FPGA.

LUTRegisterResetType Value	Description
`default`	LUT output register has default reset logic. When you generate HDL, the LUT will be synthesized as registers.
`none`	LUT output register has no reset logic. When you generate HDL, the LUT will be synthesized as a ROM.

You can specifyLUTRegisterResetTypefor the following blocks:

Gamma Correction
Lookup Table

TheNCO HDL Optimizedblock ignores this parameter.

MapPersistentVarsToRAM

With theMapPersistentVarsToRAMimplementation parameter, you can use RAM-based mapping for persistent arrays of aMATLAB Functionblock instead of mapping to registers.

MapPersistentVarsToRAM Setting	Mapping Behavior
`off`	Persistent arrays map to registers in the generated HDL code.
`on`	持续的数组变量映射到内存。为限制一下tions, seeRAM Mapping Restrictions.

RAM Mapping Restrictions

When you enable RAM mapping, a persistent array or user-defined System object™ private property maps to a block RAM when all of the following conditions are true:

Each read or write access is for a single element only. For example, submatrix access and array copies are not allowed.
Address computation logic is not read-dependent. For example, computation of a read or write address using the data read from the array is not allowed.
Persistent variables or user-defined System object private properties are initialized to 0 if they have a cyclic dependency. For example, if you have two persistent variables, A and B, you have a cyclic dependency if A depends on B, and B depends on A.
If an access is within a conditional statement, the conditional statement uses only simple logic expressions (&&,||,~) or relational operators. For example, in the following code,r1does not map to RAM:
```
if (mod(i,2) > 0) a = r1(u); else r1(i) = u; end
```
Rewrite complex conditions, such as conditions that call functions, by assigning them to temporary variables, and using the temporary variables in the conditional statement. For example, to mapr1to RAM, rewrite the previous code as follows:
```
temp = mod(i,2); if (temp > 0) a = r1(u); else r1(i) = u; end
```

The persistent array or user-defined System object private property value depends on external inputs.

For example, in the following code,bigarraydoes not map to RAM because it does not depend onu:

function z = foo(u) persistent cnt bigarray if isempty(cnt) cnt = fi(0,1,16,10,hdlfimath); bigarray = uint8(zeros(1024,1)); end z = u + cnt; idx = uint8(cnt); temp = bigarray(idx+1); cnt(:) = cnt + fi(1,1,16,0,hdlfimath) + temp; bigarray(idx+1) = idx;

RAMSizeis greater than or equal to theRAMMappingThresholdvalue.RAMSizeis the productNumElements * WordLength * Complexity.
- NumElementsis the number of elements in the array.
- WordLengthis the number of bits that represent the data type of the array.
- Complexityis 2 for arrays with a complex base type; 1 otherwise.

If any of the above conditions is false, the persistent array or user-defined System object private property maps to a register in the HDL code.

RAMMappingThreshold

The default value ofRAMMappingThresholdis 256. To change the threshold, usehdlset_param. For example, the following command changes the mapping threshold for thesfir_fixedmodel to 128 bits:

hdlset_param('sfir_fixed','RAMMappingThreshold', 128);

你也可以改变内存映射阈值the Configuration Parameters dialog box. For more information, seeRAM mapping threshold (bits)section inRAM Mapping Parameters.

Example

For an example that shows how to map persistent array variables to RAM in aMATLAB Functionblock, seeRAM Mapping With the MATLAB Function Block.

OutputPipeline

OutputPipelinelets you specify a implementation with output pipelining for selected blocks. The parameter value specifies the number of output pipeline stages (pipeline depth) in the generated code.

The following code specifies an output pipeline depth of two stages for each Sum block in the model:

sblocks = find_system(gcb, 'BlockType', 'Sum'); for ii=1:length(sblocks),hdlset_param(sblocks{ii},'OutputPipeline', 2), end;

Note

TheOutputPipelinesetting does not have any effect on blocks that do not have an output port.

When generating code for pipeline registers, HDL Coder appends a postfix string to names of input or output pipeline registers. The default postfix string is_pipe. To customize the postfix string, use thePipeline postfixoption in the Configuration Parameters dialog box, in theHDL Code Generation > Global Settings > Generaltab. Alternatively, you can use thePipelinePostfixproperty withmakehdl. For an example, seePipeline postfix.

RAMDirective

RAMDirectivelets you specify whether you want to map the RAM blocks in your Simulink model to distributed RAMs, block RAMs, or UltraRAM memory. When you select a value for this setting, HDL Coder generates aramstyleattribute in the HDL code. This attribute specifies the type of RAM memory unit that you want the synthesis tool to use when inferring the RAM blocks in your design.

RAMDirective Value	Description
`none`(default)	Do not generate the`ramstyle`attribute in the HDL code. The synthesis tool determines the type of inferred RAM for mapping the RAM blocks in your model.
`distributed`	Generate HDL attribute for mapping the RAM blocks in your model to distributed RAMs. Distributed RAMs are constructed with LUT. These RAMs are faster but occupy a larger number of LUT slices on the FPGA. This VHDL code shows the`ramstyle`attribute set to`distributed`: attribute ram_style: string; attribute ram_style of ram : signal is "distributed"; This Verilog code shows the`ramstyle`attribute set to`distributed`: (* ram_style = "distributed" *)
`block`	Generate HDL attribute for mapping the RAM blocks in your model to block RAMs. A block RAM is a dedicated memory unit on the FPGA device. The number of block RAMs available depends on the FPGA device that you are deploying the HDL code to. Sizes of block RAMs can be`4kb`,`8kb`,`16kb`, and`32kb`. To map your RAM blocks to block RAM: Specify the synthesis tool. You must target a Xilinx device that contains block RAM resources. Note If the target device does not contain block RAMs, the synthesis tool ignores this attribute and might infer the RAM as distributed RAMs or LUT slices. Enter a target frequency greater than zero. This VHDL code shows the`ramstyle`attribute set to`block`: attribute ram_style: string; attribute ram_style of ram : signal is "block"; This Verilog code shows the`ramstyle`attribute set to`block`: (* ram_style = "block" *)
`ultra`	Generate HDL attribute for mapping the RAM blocks in your model to UltraRAM memory. An UltraRAM is a dedicated memory block on the target FPGA. The number of UltraRAM memory units available depends on the FPGA device that you are deploying the HDL code to. UltraRAM units are larger than block RAMs and can be as large as`500Mb`in size. To map your RAM blocks to UltraRAM: Specify Xilinx Vivado^®as the synthesis tool. You must target a Xilinx device that contains UltraRAM resources, such as Virtex^®UltraScale+™. Note If the target device does not contain UltraRAM memory, the synthesis tool ignores this attribute and might infer the RAM as distributed RAMs or LUT slices. To map the RAM blocks to block RAMs instead, setRAMDirectiveto`block`. Enter a target frequency greater than zero. The RAM blocks in your design must follow a fixed-read behavior and have a single clock interface. In theHDL RAMslibrary, except forDual Port RAMandDual Rate Dual Port RAMblocks, you can map all other RAM blocks to UltraRAM. 内存块必须没有初始值的规范ified. When you use the RAM System blocks such asSingle Port RAM System,Specify the RAM initial valuemust be set to`0`. On device reset, all memory locations in the UltraRAM are initialized to zero. This VHDL code shows the`ramstyle`attribute set to`ultra`: attribute ram_style: string; attribute ram_style of ram : signal is "ultra"; This Verilog code shows the`ramstyle`attribute set to`ultra`: (* ram_style = "ultra" *)

Set RAMDirective for RAM Blocks

In theHDL RAMslibrary, except for theDual Rate Dual Port RAM, you can specify theRAMDirectiveproperty for all other RAM blocks.

To setRAMDirectivefor a RAM block from the HDL Block Properties dialog box:

Right-click the RAM block.
SelectHDL Code>HDL Block Properties.
ForRAMDirective, selectnone,distributed,block, orultra.

Note

For theDual Port RAMblock, you cannot specifyultraas theRAMDirectivebecause the block does not have a fixed read behavior.

To setRAMDirectivefor a block from the command line, usehdlset_param. For example, to setRAMDirectivetoultrafor aSingle Port RAMblock inside a subsystem,my_dut:

hdlset_param(“我的_dut/Single Port RAM','RAMDirective',“超”);

See alsohdlset_param.

ResetType

Use theResetTypeblock parameter to suppress reset logic generation.

ResetType Value Description

ResetType Value	Description
`default`	Generate reset logic.
`none`	Do not generate reset logic. Reset is not applied to generated registers. Therefore, mismatches between Simulink and the generated code occur for some number of samples during the initial phase, when registers are not fully loaded. To avoid test bench errors during the initial phase, determine the number of samples required to fully load the registers. Then, set theIgnore output data checking (number of samples)option accordingly. See alsoIgnore output data checking (number of samples)inTest Bench Stimulus and Output Parameters.

default

Generate reset logic.

none

Do not generate reset logic.

Reset is not applied to generated registers. Therefore, mismatches between Simulink and the generated code occur for some number of samples during the initial phase, when registers are not fully loaded.

To avoid test bench errors during the initial phase, determine the number of samples required to fully load the registers. Then, set theIgnore output data checking (number of samples)option accordingly. See alsoIgnore output data checking (number of samples)inTest Bench Stimulus and Output Parameters.

You can specifyResetTypefor the following blocks:

Chart
Convolutional Deinterleaver
Convolutional Interleaver
Delay
Delay(DSP System Toolbox™)
General Multiplexed Deinterleaver
General Multiplexed Interleaver
MATLAB Function
MATLAB System
备忘录ry
Tapped Delay
Truth Table
Unit Delay Enabled
Unit Delay

Reset Logic for Optimizations in the MATLAB Function Block

When you setResetTypetononefor aMATLAB Functionblock, HDL Coder does not generate reset logic for persistent variables in the MATLAB^®code.

However, if you specify other optimizations for the block, the coder may insert registers that use reset logic. The coder does not suppress reset logic generation for these registers. Therefore, if you setResetTypetononealong with other block optimizations, your generated code may have a reset port at the top level.

How to Suppress Reset Logic Generation

To suppress reset logic generation for a block using the UI:

Right-click the block and selectHDL Code>HDL Block Properties.
ForResetType, selectnone.

To suppress reset logic generation, on the command line, enter:

hdlset_param(path_to_block,'ResetType','none')

For example, to suppress reset logic generation for a Unit Delay block,UnitDelay1, within a subsystem,mySubsys, on the command line, enter:

hdlset_param('mySubsys/UnitDelay1','ResetType','none');

Specify Synchronous or Asynchronous Reset

To specify a synchronous or asynchronous reset, use theResetTypemodel-level parameter. For details, seeReset typeinReset Settings and Parameters.

SerialPartition

Use this parameter on Min/Max blocks to specify partitions for a serial cascade architecture. The default setting uses the minimum number of partitions.

To Generate This
Architecture... Set SerialPartition to...

Cascade-serial with explicitly specified partitioning [p1 p2 p3...pN]: a vector ofNintegers, whereNis the number of serial partitions. Each element of the vector specifies the length of the corresponding partition. The sum of the vector elements must be equal to the length of the input data vector. The values of the vector elements must be in descending order, except the last two elements can be equal. For example, for an input of 8 elements, partitions[5 3]or[4 2 2]are legal, but the partitions[2 2 2 2]or[3 2 3]raise an error at code generation time.

Cascade-serial with automatically optimized partitioning 0

To Generate This Architecture...	Set SerialPartition to...
Cascade-serial with explicitly specified partitioning	`[p1 p2 p3...pN]`: a vector of`N`integers, where`N`is the number of serial partitions. Each element of the vector specifies the length of the corresponding partition. The sum of the vector elements must be equal to the length of the input data vector. The values of the vector elements must be in descending order, except the last two elements can be equal. For example, for an input of 8 elements, partitions`[5 3]`or`[4 2 2]`are legal, but the partitions`[2 2 2 2]`or`[3 2 3]`raise an error at code generation time.
Cascade-serial with automatically optimized partitioning	`0`

This property is also used for serial filter architectures. For how to configure filter blocks, seeSerialPartition.

SharingFactor

UseSharingFactorto specify the number of functionally equivalent resources to map to a single shared resource. The default is 0. SeeResource Sharing.

SoftReset

Use theSoftResetblock parameter to specify whether to generate hardware-friendly synchronous reset logic, or local reset logic that matches the Simulink simulation behavior. This property is available for theUnit Delay Resettableblock orUnit Delay Enabled Resettableblock.

SoftReset Value	Description
`off`(default)	Generate local reset logic that matches the Simulink simulation behavior.
`on`	Generate synchronous reset logic for the block. This option generates code that is more efficient for synthesis, but does not match the Simulink simulation behavior.

WhenSoftResetset to'off', the following code is generated for aUnit Delay Resettableblock :

always @(posedge clk or posedge reset) begin : Unit_Delay_Resettable_process if (reset == 1'b1) begin Unit_Delay_Resettable_zero_delay <= 1'b1; Unit_Delay_Resettable_switch_delay <= 2'b00; end else begin if (enb) begin Unit_Delay_Resettable_zero_delay <= 1'b0; if (UDR_reset == 1'b1) begin Unit_Delay_Resettable_switch_delay <= 2'b00; end else begin Unit_Delay_Resettable_switch_delay <= In1; end end end end assign Unit_Delay_Resettable_1 = (UDR_reset || Unit_Delay_Resettable_zero_delay ? 1'b1 : 1'b0); assign out0 = (Unit_Delay_Resettable_1 == 1'b1 ? 2'b00 : Unit_Delay_Resettable_switch_delay);

WhenSoftResetset to'on', the following code is generated for aUnit Delay Resettableblock :

always @(posedge clk or posedge reset) begin : Unit_Delay_Resettable_process if (reset == 1'b1) begin Unit_Delay_Resettable_reg <= 2'b00; end else begin if (enb) begin if (UDR_reset != 1'b0) begin Unit_Delay_Resettable_reg <= 2'b00; end else begin Unit_Delay_Resettable_reg <= In1; end end end end assign out0 = Unit_Delay_Resettable_reg;

StreamingFactor

Number of parallel data paths, or vectors, to transform into serial, scalar data paths by time-multiplexing serial data paths and sharing hardware resources. The default is 0, which implements fully parallel data paths. See alsoStreaming.

UsePipelines

You can use this mode withProductblocks inDivideandReciprocalmodes. This property becomes available when you set the HDL architecture for the blocks toShiftAdd. This architecture uses a non-restoring division algorithm that performs multiple shift and add operations to compute the quotient. TheShiftAddarchitecture provides improved accuracy compared to the Newton-Raphson approximation method.

When you use theShiftAddarchitecture, you can use theUsePipelinesimplementation parameter to specify whether to use a pipelined or non-pipelined implementation of the non-restoring division.

UsePipelines Setting	Mapping Behavior
`on`(default)	Use a pipelined implementation of the non-restoring shift and add operation forDivideandReciprocalblocks. This setting adds more delays to your design but achieves a higher maximum clock frequency on the target FPGA device. The number of pipelines inserted matches the number of iterations that the algorithm requires to compute the quotient or reciprocal.
`off`	Use a non-pipelined implementation of the non-restoring shift and add operation forDivideandReciprocalblocks. This setting does not add delays to your design. As division and reciprocal are resource-intensive operations, to achieve higher clock frequencies on the target FPGA, setUsePipelinesto`on`.

Set UsePipelines for Divide and Reciprocal Blocks

To setUsePipelinesfor a subsystem from the HDL Block Properties dialog box:

Right-click the subsystem.
SelectHDL Code>HDL Block Properties.
ForUsePipelines, selectonoroff.

To setUsePipelinesfor a block from the command line, usehdlset_param. For example, to turn offUsePipelinesfor aDivideblock inside a subsystem,my_dut:

hdlset_param(“我的_dut/divide','UsePipelines','off');

See alsohdlset_param.

UseRAM

TheUseRAMimplementation parameter enables using RAM-based mapping for a block instead of mapping to a shift register.

UseRAM Setting Mapping Behavior

UseRAM Setting	Mapping Behavior
`off`	The delay maps to a shift register in the generated HDL code, except in one case. For details, seeEffects of Streaming and Distributed Pipelining.
`on`	The delay maps to a dual-port RAM block when the following conditions are true: Initial value of the delay is zero. TheDelayblock does not have an external reset or enable port. Delay length> 4. Delay has one of the following set of numeric and data type attributes: (a) Real scalar with a non-floating-point data type (such as signed integer, unsigned integer, fixed point, or Boolean) (b) Complex scalar with real and imaginary parts that use non-floating-point data type (c) Vector where each element is either (a) or (b) `RAMSize`is greater than or equal to the`RAMMappingThreshold`value.`RAMSize`is the product`DelayLength * WordLength * ComplexLength`. `DelayLength`is the number of delays that the Delay block specifies. `WordLength`is the number of bits that represent the data type of the delay. `ComplexLength`is 2 for complex signals; 1 otherwise. If any condition is false, the delay maps to a shift register in the HDL code unless it merges with other delays to map to a single RAM. For more information, seeMapping Multiple Delays to RAM.

off

The delay maps to a shift register in the generated HDL code, except in one case. For details, seeEffects of Streaming and Distributed Pipelining.

on

The delay maps to a dual-port RAM block when the following conditions are true:

Initial value of the delay is zero.
TheDelayblock does not have an external reset or enable port.
Delay length> 4.
Delay has one of the following set of numeric and data type attributes:
- (a) Real scalar with a non-floating-point data type (such as signed integer, unsigned integer, fixed point, or Boolean)
- (b) Complex scalar with real and imaginary parts that use non-floating-point data type
- (c) Vector where each element is either (a) or (b)
RAMSizeis greater than or equal to theRAMMappingThresholdvalue.RAMSizeis the productDelayLength * WordLength * ComplexLength.
- DelayLengthis the number of delays that the Delay block specifies.
- WordLengthis the number of bits that represent the data type of the delay.
- ComplexLengthis 2 for complex signals; 1 otherwise.

If any condition is false, the delay maps to a shift register in the HDL code unless it merges with other delays to map to a single RAM. For more information, seeMapping Multiple Delays to RAM.

This implementation parameter is available for theDelayblock in the Simulink Discrete library and theDelay(DSP System Toolbox)block in the DSP System Toolbox Signal Operations library.

Mapping Multiple Delays to RAM

HDL Coder can also merge several delays of equal length into one delay and then map the merged delay to a single RAM. This optimization provides the following benefits:

Increased occupancy on a single RAM
Sharing of address generation logic, which minimizes duplication of identical HDL code
Mapping of delays to a RAM when theindividualdelays do not satisfy the threshold

The following rules control whether or not multiple delays can merge into one delay:

The delays must:
- Be at the same level of the subsystem hierarchy.
- Use the same compiled sample time.
- HaveUseRAMset toon, or be generated by streaming or resource sharing.
- Have the sameResetTypesetting, which cannot benone.
The total word length of the merged delay cannot exceed 128 bits.
TheRAMSizeof the merged delay is greater than or equal to theRAMMappingThresholdvalue.RAMSizeis the productDelayLength * WordLength * VectorLength * ComplexLength.
- DelayLengthis the total number of delays.
- WordLengthis the number of bits that represent the data type of the merged delay.
- VectorLengthis the number of elements in a vector delay.VectorLengthis 1 for a scalar delay.
- ComplexLengthis 2 for complex delays; 1 otherwise.

Example of Multiple Delays Mapping to a Block RAM

RAMMappingThresholdfor the following model is 100 bits.

The Delay and Delay1 blocks merge and map to a dual-port RAM in the generated HDL code by satisfying the following conditions:

Both delay blocks:
- Are at the same level of the hierarchy.
- Use the same compiled sample time.
- HaveUseRAMset toonin the HDL block properties dialog box.
- Have the sameResetTypesetting ofdefault.
The total word length of the merged delay is 28 bits, which is below the 128-bit limit.
TheRAMSizeof the merged delay is 112 bits (4 delays * 28-bit word length), which is greater than the mapping threshold of 100 bits.

When you generate HDL code for this model, HDL Coder generates additional files to specify RAM mapping. The coder stores these files in the same source location as other generated HDL files, for example, thehdlsrcfolder.

Effects of Streaming and Distributed Pipelining

WhenUseRAMisofffor a Delay block, HDL Coder maps the delay to a shift register by default. However, the coder changes theUseRAMsetting toonand tries to map the delay to a RAM under the following conditions:

Streaming isenabledfor the subsystem with theDelayblock.
Distributed pipelining isdisabledfor the subsystem with theDelayblock.

Suppose that distributed pipelining isenabledfor the subsystem with theDelayblock.

WhenUseRAMisoff, theDelayblock participates in retiming.
WhenUseRAMison, theDelayblock does not participate in retiming. HDL Coder does not break up a delay marked for RAM mapping.
Consider a subsystem with twoDelayblocks, threeConstantblocks, and threeProductblocks:

WhenUseRAMisonfor the Delay block on the right, that delay does not participate in retiming.

The following summary describes whether or not HDL Coder tries to map a delay to a RAM instead of a shift register.

`UseRAM`Setting for the Delay Block	优化支持Subsystem with Delay Block
`UseRAM`Setting for the Delay Block	Distributed Pipelining Only	Streaming Only	Both Distributed Pipelining and Streaming
On	Yes	Yes	Yes
从	No	Yes, because mapping to a RAM instead of a shift register can provide an area-efficient design.	No

VariablesToPipeline

Warning

VariablesToPipelineis not recommended. Usecoder.hdl.pipelineinstead.

The VariablesToPipeline parameter enables you to insert a pipeline register at the output of one or more MATLAB variables. Specify a list of variables as a character vector, with spaces separating the variables.