Considerations

When you map your DUT ports to AXI4 or AXI4-Lite interfaces:

Map Scalar Ports to AXI4 Slave Interface

When you use scalar data types at the DUT interface ports, you can directly map the interface ports to AXI4 or AXI4-Lite interfaces. The code generator assigns a unique address to each data port that you want to map to the AXI4 interface.

For an example that shows how to map scalar ports to AXI4-Lite interfaces, open the modelhdlcoder_led_blinking。

open_system('hdlcoder_led_blinking'）

In this model, the subsystemled_counteris the hardware subsystem. It models a counter that blinks the LEDs on an FPGA board. Two input ports,Blink_frequencyandBlink_direction，，，，are control ports that determine the LED blink frequency and direction. All the blocks outside of the subsystemled_counterare for software implementation.

在Si万博1manbetxmulink中^®，，，，you can use theSlider Gainblock or theManual Switch块以调整硬件子系统的输入值。ARM处理器通过写入嵌入式软件中的Axi接口可访问寄存器来控制生成的IP核心。硬件子系统的输出端口连接到LED硬件。您可以使用输出端口Read_back将数据读回处理器。

When you run theIP核心生成工作流程，在设置目标接口task, you see that the portsBlink_frequency，，，，Blink_direction，，，，andRead_backmap to AXI4-Lite interfaces.

要了解有关此示例的更多信息，请参见：

Map Vector Ports to AXI4 Slave Interface

When you use vector data types at the DUT interface ports, you can directly map the interface ports to AXI4 or AXI4-Lite interfaces. The code generator assigns a unique address for each data port that you want to map to the AXI4 interface.

When you map vector ports, HDL Coder uses additional strobe registers for each port to maintain the synchronization with the IP core algorithm logic. For input ports, the strobe registers control the enable signals for a set of shadow registers, making the IP core algorithm logic see the updated vector elements simultaneously. For output ports, the strobe registers make sure that the vector data to be read is captured synchronously.

对于显示如何将向量端口映射到AXI4-LITE接口的示例，请打开模型hdlcoder_led_vector。

open_system('hdlcoder_led_vector'）

In this model, the subsystemDUTimplements the LED blinking algorithm and has vector output ports. When you run theIP核心生成workflow, you see that the input ports and output ports map to AXI4-Lite interfaces in the设置目标接口task.

To learn more, seeIP核心生成Workflow with a MicroBlaze processor: Xilinx Kintex-7 KC705。

地图总线数据类型到AXI4从接口

当您在DUT接口端口上使用总线数据类型时，您可以将接口端口直接映射到AXI4或AXI4-LITE接口。

映射总线数据类型时，HDL编码器将为要映射到AXI4接口的每个数据端口分配一个唯一地址。顶级和子级别的总线没有寄存器偏移地址。单独的标量或矢量总线元素的地址映射不是连续的。

Specify Initial Value of AXI4 Slave Registers

When you run theIP核心生成workflow or the万博1manbetxSimulink实时FPGA I/O工作流程，您可以为映射到AXI4从寄存器的输入端口指定初始值。您可以在映射到这些目标接口时指定初始值：

By default, the initial value is zero. To specify a nonzero value:

这specified value is saved on the DUTInportblocks as the HDL block propertyioInterfaceOptionsin theTarget Specification标签。例如，如果将DUT输入端口映射到AXI4-LITE接口，请设置RegisterInitialValue至5，，，，and then run the设置目标接口任务。ioInterfaceOptions该输入端口的属性用值保存{'RegisterInitialValue'，'5'}。

To view theioInterfaceOptions价值，如果通往DUT端口的完整途径是hdlcoder_led_blinking/led_counter/LED， 进入：

hdlget_param('hdlcoder_led_blinking/led_counter/led'，，，，...'ioInterfaceOptions'）

Specify the initial value for scalar ports.

HDLSET_PARAM('hdlcoder_led_blinking/led_counter/led'，，，，...'ioInterfaceOptions'，，，，{'RegisterInitialValue'，，，，'5'}）;

To set the initial value for a bus, specify a struct whose field names match the bus element names. For example,

You can also specify the initial value by using a variable defined in the MATLAB^®workspace. For example:

bus1_initialvalue = struct('scalar_in1',1,'scalar_in2',2,'scalar_in3',3,'scalar_in4',4,'vector_in',[1 3])

Read Back Value of AXI4 Slave Interfaces

When you run theIP核心生成工作流程，您可以使用AXI4从接口读取写入AXI4从寄存器的值。例如，您可以通过使用该值来读取写入AXI4从寄存器的值devmem在ARM处理器的Linux控制台中命令。如果已安装HDL Verifier™，则可以将MATLAB用作Axi Master IP来读取值。

要使用此功能，生成RTL代码和IP核心任务IP核心生成workflow, select theEnable read back on AXI4 slave write registers复选框，然后运行生成RTL代码和IP核心task

运行此任务时，HDL编码器将保存在模型上启用的读取背部设置。在DUT子系统的HDL块属性中IP Core Parameter部分Target Specificationtab, you see a parameterAXI4RegisterReadbackset toon。如果导出HDL Workflow Advisor运行到脚本，则会看到通过使用该设置保存在模型上HDLSET_PARAM。

HDLSET_PARAM('hdlcoder_led_vector/DUT'，，，，'Axi4RegisterReadBack'，，，，'上'）;

这些示例显示了如何通过使用devmem带有Putty™等程序的Linux控制台命令。

To read back values when mapping scalar ports to AXI4 interfaces, you first write values to the AXI4 registers, and then read back the values. You can see the memory address of the AXI4 registers in the IP Core Generation report.

To read back values when mapping vector ports to AXI4 interfaces, you first write to the AXI4 registers, then write the strobe register address with0x1，，，，and then read back the values. You can see the memory address of the AXI4 registers and the strobe register in the IP Core Generation report.

优化AXI4从属阅读逻辑

When your model contains several output registers and you want to read back data from multiple AXI4 slave registers, the read back logic becomes a long mux chain that can reduce the synthesis frequency. If you select theEnable readback on AXI4 slave write registerssetting in the生成RTL代码和IP核心task, HDL Coder adds a mux for each AXI4 register in the Address Decoder logic. As the number of AXI4 slave registers increases, the mux chain becomes longer, which further reduces the synthesis frequency.

You can optimize the readback logic and achieve the target frequency that you want. When you run theIP核心生成工作流程，在生成RTL代码和IP核心任务，您会看到设置AX4 slave port to pipeline register ratio。这default value of this setting isauto。This setting indicates how many AXI4 slave registers a pipeline register is inserted for. For example, anAX4 slave port to pipeline register ratioof20means that one pipeline register is inserted for every20Axi奴隶寄存器。这auto设置意味着代码生成器根据您指定的端口数量和合成工具插入AXI4从端口的一定数量的管道。您可以禁用此设置或在5and50for this ratio.

When you run this task, HDL Coder saves the value that you specified for the setting on the model. In the HDL Block Properties of the DUT Subsystem, on theIP Core Parameter部分Target Specificationtab, you see a parameterAX4SlavePortToPipelineRegisterRatio设置为您指定的值。如果导出HDL Workflow Advisor运行到脚本，则会看到通过使用该设置保存在模型上HDLSET_PARAM。

HDLSET_PARAM('hdlcoder_led_vector/DUT'，，，，...'AXI4SlavePortToPipelineRegisterRatio'，，，，'20'）;