主要内容

IntelSoC Devices

在英特尔生成和部署HDL代码和嵌入式软件®SoC Devices

HDL Coder™可以生成IP核心，将其集成到您的QSYS项目中，并编程Intel硬件。使用嵌入式编码器®, you can generate and build the embedded software, and run it on the ARM®processor. SeeHardware-Software Co-Design Workflow for SoC Platforms。

To deploy your design to the Intel SoC device, you must install theHDL编码器支持包适万博1manbetx用于英特尔SOC设备。有关安装信息，请参阅HDL编码器支持硬件万博1manbetx。

Classes

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hdlcoder.Board Board registration object that describes SoC custom board
hdlcoder.workflowconfig 配置HDL代码生成和部署工作流程
hdlcoder.sefercedesign Reference design registration object that describes SoC reference design

Functions

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socExportReferenceDesign HDL工作流顾问的导出自定义参考设计
addExternalIOInterface Define external IO interface for board object
addExternalPortInterface Define external port interface for board object
addInternalIOInterface Add and define internal IO interface between generated IP core and existing IP cores
addAXI4MasterInterface 添加并定义AXI4主界面
addAXI4SlaveInterface 添加并定义AXI4从接口
addAXI4StreamInterface Add AXI4-Stream interface
addAXI4StreamVideoInterface Add AXI4-Stream Video interface
addClockInterface Add clock and reset interface
AddCustomedKdesign SpecifyXilinxEDK MHS project file
AddCustomqsysdesign SpecifyAlteraQsys project file
addCustomVivadoDesign SpecifyXilinxVivado导出块设计TCL文件
addIPRepository Include IP modules from your IP repository folder in your custom reference design
addParameter Add and define custom parameters for your reference design
validateReferenceDesign 在参考设计对象中检查属性值
验证板 Check property values in board object
CallbackCustomProgrammingMethod Function handle for custom callback function that gets executed during Program Target Device task in the Workflow Advisor
嵌入式codersuppo万博1manbetxrtpackage 指定是否使用嵌入式编码器support package
PostBuildBitstreamFcn 在HDL Workflow Advisor中构建FPGA bitstream任务后执行的回调函数的函数句柄
PostCreateProjectFCN Function handle for callback function that gets executed after Create Project task in the HDL Workflow Advisor
PostSWInterfaceFcn Function handle for custom callback function that gets executed after Generate Software Interface task in the HDL Workflow Advisor
PostTargetInterfaceFcn Function handle for callback function that gets executed after Set Target Interface task in the HDL Workflow Advisor
PostTargetReatedendesignfcn Function handle for callback function that gets executed after Set Target Reference Design task in the HDL Workflow Advisor

Topics

Related Information

Troubleshooting

Resolve Timing Failures in IP Core Generation and Simulink Real-Time FPGA I/O Workflows

Resolve timing failures in Build FPGA Bitstream step of IP Core Generation Workflow or Simulink Real-Time FPGA I/O Workflow for Vivado-Based Boards.