万博1manbetxReal-TimeFPGA I/O Modules

Generate and deploy HDL code on万博1manbetx^®Real-Time™FPGA I/O Modules (requiresSimulink Real-Time)

You can generate an FPGA programming file andSimulink Real-TimeFPGA I/O interface for deployment on a Speedgoat board. SeeIP Core Generation Workflow for Speedgoat Simulink-Programmable I/O Modules.

Classes

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Board and Workflow

`hdlcoder.Board`	Board registration object that describes SoC custom board
`hdlcoder.WorkflowConfig`	Configure HDL code generation and deployment workflows
`hdlcoder.ReferenceDesign`	Reference design registration object that describes SoC reference design

Functions

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Export Reference Design

socExportReferenceDesign 导出自定义reference design for HDL Workflow Advisor

Add Interfaces

`addExternalIOInterface`	Define external IO interface for board object
`addExternalPortInterface`	Define external port interface for board object
`addInternalIOInterface`	Add and define internal IO interface between generated IP core and existing IP cores
`addAXI4MasterInterface`	Add and define AXI4 Master interface
`addAXI4SlaveInterface`	添加和定义AXI4奴隶接口
`addAXI4StreamInterface`	Add AXI4-Stream interface
`addAXI4StreamVideoInterface`	Add AXI4-Stream Video interface
`addClockInterface`	Add clock and reset interface

Board and Reference Design

`addCustomEDKDesign`	SpecifyXilinxEDK MHS project file
`addCustomQsysDesign`	SpecifyAlteraQsys project file
`addCustomVivadoDesign`	SpecifyXilinxVivadoexported block design Tcl file
`addIPRepository`	Include IP modules from your IP repository folder in your custom reference design
`addParameter`	Add and define custom parameters for your reference design
`validateReferenceDesign`	Check property values in reference design object
`validateBoard`	Check property values in board object

Topics

IP Core Generation Workflow for Speedgoat Simulink-Programmable I/O Modules

Use the IP Core Generation workflow with Speedgoat I/O modules and embed the IP core into the reference design.

Program Target FPGA Boards or SoC Devices

How to program the target Intel or Xilinx Hardware.

Generate Simulink Real-Time Interface Subsystem for Simscape Two-Level Converter Model

Generate HDL code and Simulink Real-Time interface model from Simscape™ models.

Speedgoat FPGA Support with HDL Workflow Advisor

Implementing Simulink algorithms on FPGAs on board Speedgoat FPGA I/O modules.

Related Information

Custom IP Core Generation

Custom Reference Design

Troubleshooting

Resolve Timing Failures in IP Core Generation and Simulink Real-Time FPGA I/O Workflows

Resolve timing failures in Build FPGA Bitstream step of IP Core Generation Workflow or Simulink Real-Time FPGA I/O Workflow for Vivado-Based Boards.

Featured Examples

FPGA Programming and Configuration on Speedgoat Simulink-Programmable I/O Modules

Select and run HDL code generation and synthesis workflow for a Speedgoat target device.

Open Script

Deploy Simscape Buck Converter Model to Speedgoat IO Module Using HDL Workflow Script

Deploy buck converter modeled in Simscape to Speedgoat IO modules using HDL Workflow script.

Open Script

Hardware-in-the-Loop Implementation of Simscape Model on Speedgoat FPGA I/O Modules

Synthesize and generate FPGA bitstream from a Simscape™ half-wave rectifier model and download the bitstream to a Speedgoat FPGA I/O 334-325K target for Hardware-in-the-Loop (HIL) implementation.

Open Script

HDL Coder Documentation

万博1manbetx

Deploying 5G NR Wireless Communications on FPGAs: A Complete MATLAB and Simulink Workflow

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