HDL Coder
HDL Coder™ generates portable, synthesizable VHDL®and Verilog®code from MATLAB®functions, Simulink®models, and Stateflow®charts. The generated HDL code can be used for FPGA programming or ASIC prototyping and design.
HDL Coder provides a workflow advisor that automates the programming of Xilinx®and Altera®FPGAs. You can control HDL architecture and implementation, highlight critical paths, and generate hardware resource utilization estimates. HDL Coder provides traceability between your Simulink model and the generated Verilog and VHDL code, enabling code verification for high-integrity applications adhering to DO-254 and other standards.
Getting Started
学习基本的HDL编码器
HDL Code Generation from MATLAB
Generate HDL Code from MATLAB algorithms
HDL Code Generation from Simulink
Generate HDL code from Simulink models
Hardware-Software Codesign
Deploy partitioned hardware and software on a target hardware platform
Supported Hardware
Support for third-party hardware, such as Altera and Xilinx FPGA boards