Model Info

Display model properties and text in model

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Library:
Simulink / Model-Wide Utilities
HDL Coder / Model-Wide Utilities

Description

TheModel Infoblock displays model properties and text about a model on the mask of the block. Use theModel Infoblock dialog box to specify the content and format of the text that the block displays. You can select model properties to display on the block. In the text displayed on the block mask, Simulink^®将属性名称替换为模型中属性的当前值。

Parameters

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`指定要显示的文本和属性`— Content and format of the text to display
不default

Use theEnter text and tokens to display on Model Info blockedit box to specify the text and properties to display.

In the edit box, enter any text you want to display on the block mask. Edit the default textModel Info。
To display a model property on the block mask, select a property in theModel propertieslist and click the right arrow button.
该块添加了表单的令牌%to the edit box. In the text the block mask displays, Simulink replaces the token with the value of the property.
1. For example, if you selectDescription在里面Model propertieslist and click the right arrow button, then the token
```
%
```
  appears in the right edit box.
2. 您可以在模型属性之前添加一些解释性文本，例如“Model description:”.
3. When you clickApply或者好的, Simulink displays your new text and the current value of the model property on the block mask in the Model Editor.
SeeAccess Model Information Programmatically为描述模型的属性。

If you are interested in source control information, for a flexible interface to source control tools, use a project. SeeSource Control in Projects。

Model Examples

使用可变传输延迟现象的模拟系统

Two cases where you can use Simulink® to model variable transport delay phenomena.

Open Model

块特征

Data Types
Direct Feedthrough	`不`
Multidimensional Signals	`不`
Variable-Size Signals	`不`
Zero-Crossing Detection	`不`

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

TheModel Infoblock is ignored during code generation.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™提供了影响HDL实现和合成逻辑的其他配置选项。

Best Practices

When usingModel Infoblocks in models targeted for HDL code generation, consider using only ASCII characters in the text that you enter to display on theModel Info堵塞。如果您在生成的HDL代码中具有非ASCII字符，则RTL仿真和合成工具可能无法编译代码。

HDL Architecture

This block has a single, default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is`0`。有关更多详细信息，请参阅ConstrainedOutputPipeline(HDL Coder)。
InputPipeline	输入管道阶段的数量要插入生成的代码中。分布式管道和约束输出管道可以移动这些寄存器。默认值为`0`。有关更多详细信息，请参阅InputPipeline(HDL Coder)。
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is`0`。有关更多详细信息，请参阅OutputPipeline(HDL Coder)。

Model Info

Description

Parameters

`指定要显示的文本和属性`— Content and format of the text to display
不default

Model Examples

使用可变传输延迟现象的模拟系统

块特征

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

PLC Code Generation
Generate Structured Text code using Simulink® PLC Coder™.

See Also

Topics

Simulink Documentation

万博1manbetx

Model-Based Design for Embedded Control Systems

Model Info

Description

Parameters

指定要显示的文本和属性— Content and format of the text to display不default

Model Examples

使用可变传输延迟现象的模拟系统

块特征

Extended Capabilities

C/C++ Code GenerationGenerate C and C++ code using Simulink® Coder™.

HDL Code GenerationGenerate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

PLC Code GenerationGenerate Structured Text code using Simulink® PLC Coder™.

See Also

Topics

Simulink Documentation

万博1manbetx

Model-Based Design for Embedded Control Systems

`指定要显示的文本和属性`— Content and format of the text to display
不default

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

PLC Code Generation
Generate Structured Text code using Simulink® PLC Coder™.