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dlhdl.buildProcessor

Build and generate custom processor IP

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    Syntax

    dlhdl.buildProcessor
    dlhdl.buildProcessor(processorconfigobject)
    dlhdl.buildProcessor(processorconfigobject,Name,Value)

    Description

    example

    dlhdl.buildProcessor背包es a bitstream for the defaultdlhdl.ProcessorConfigobject.

    dlhdl.buildProcessor(processorconfigobject)背包es a bitstream for theprocessorconfigobjectobject.

    dlhdl.buildProcessor(processorconfigobject,Name,Value)背包es a bitstream for theprocessorconfigobjectobject, with additional options specified by one or moreName,Valuearguments.

    Examples

    Generate Custom Bitstream for Custom Processor Configuration

    创建一个custom processor configuration. Generate a bistream for the custom processor configuration.

    创建一个dlhdl.ProcessorConfigobject. Save the object inhPC.

    hPC = dlhdl.ProcessorConfig

    Generate a custom bitstream forhPC

    dlhdl.buildProcessor(hPC)

    Generate Custom Bitstream and Specify Project Folder Name, Deep Learning Processor IP Core Name, and Target Code Generation language

    创建一个custom deep learning processor configuration. When you generate code specify the project folder name, deep learning processor IP core name, and target code generation language.

    hPC = dlhdl.ProcessorConfig; dlhdl.buildProcessor(hPC,'ProjectFolder','fconlyprocessor_prj',...'ProcessorName','fconlyprocessor','HDLCoderConfig',{'TargetLanguage','Verilog'});

    Input Arguments

    collapse all

    Name of the custom processor configuration object, specified as a variable of typedlhdl.Processorconfig.

    Example:dlhdl.buildProcessor(hPC)

    Name-Value Arguments

    Specify optional pairs of arguments asName1=Value1,...,NameN=ValueN, whereNameis the argument name andValueis the corresponding value. Name-value arguments must appear after other arguments, but the order of the pairs does not matter.

    Before R2021a, use commas to separate each name and value, and encloseNamein quotes.

    Example:

    Name of project folder where generated files are saved

    Example:'ProjectFolder', 'fconlyprocessor_prj'

    Name of generated deep learning processor IP core

    Example:'ProcessorName', 'fconlyprocessor'

    Specify whether to generate VHDL or Verilog code.

    Example:'HDLCoderConfig',{'TargetLanguage','Verilog'}

    Version History

    Introduced in R2020b

    See Also

    Topics