FPGA-in-the-Loop

Test design in hardware (requires HDL Verifier™)

When you generate HDL code in HDL Workflow Advisor, you can load the generated code into an FPGA board. You can optionally generate a Simulink^®model that includes anFPGA-in-the-Loopblock that communicates with your HDL design running on the FPGA board. The model also includes your original Simulink stimulus generation, behavioral model, and blocks that display or analyze output data. The model compares the output of theFPGA-in-the-Loop对源子系统的输出块。

To use this feature, you must install the HDL Verifier Support Package for Xilinx^®or Altera^®FPGA boards. SeeHDL Verifier Supported Hardware(HDL Verifier).

Classes

hdlcoder.WorkflowConfig Configure HDL code generation and deployment workflows

Model Settings

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Test Bench Generation Output and Postfix

Test Bench Generation Output Parameters

Test Bench Postfix Parameters

Multi-file test bench

Test Bench Inputs and Output

Clock and Reset Input Parameters for Testbench

Setup and Hold Time Parameters for Testbench

Test Bench Stimulus and Output Parameters

Topics

FIL Simulation with HDL Workflow Advisor for Simulink(HDL Verifier)
Generate an FPGA-in-the-loop model using HDL Workflow Advisor.
FPGA-in-the-Loop Simulation Workflows(HDL Verifier)
Choose between generating a block or System object™, and decide whether to use the FIL Wizard or HDL Workflow Advisor.
Run HDL Workflow with a Script
Export, import, or configure an HDL Workflow CLI command script.
Getting Started with the HDL Workflow Command-Line Interface
This example shows how to use the HDL Workflow Advisor to run HDL workflows from the command-line and the 'Export to script' functionality.

Related Information

FPGA-in-the-Loop(HDL Verifier)
FPGA Board Customization