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5

answers

8 votes
3.1k views

What are MIL, SIL, PIL, and HIL, and how do they integrate with the Model-Based Design approach?

Asked byMathWorks Support Team on 2 Jan 2019

Latest activity Commented onbyM. KORAY YILMAZon 19 Apr 2022 at 13:06

Accepted AnswerbyMathWorks Support Team

Verification, Validation, and Test Simulink Test Test Execution SIL, PIL, and HIL Tests

1

answer

0 votes
3 views

Why is my FFT HDL Optimized block running slower in FIL than Simulink?

Asked byAdil Zafar on 17 Feb 2022

Latest activity EditedbyBharath Venkataraman on 24 Feb 2022

Accepted AnswerbyBharath Venkataraman

Code Generation HDL Verifier Verification with FPGA Hardware FPGA-in-the-Loop

0

answers

0 votes
2 views

Unexpected unknown exception from MEX file...

Asked byEdwin Fonkwe Fongang on 6 Jan 2022

Code Generation HDL Verifier Verification with FPGA Hardware FPGA-in-the-Loop

1

answer

0 votes
2 views

Error in FIL simulation at the second time it's running

Asked byKyoji Marumoto on 14 Sep 2021

Latest activity EditedbyKyoji Marumotoon 21 Sep 2021

Code Generation HDL Verifier Verification with FPGA Hardware FPGA-in-the-Loop

0

answers

0 votes
1 view

What verison of MatLab Software support Microsemi/Microchip FPGAs with what versions of Libero SOC? Also, are Polarfire and PolarfireSOC supported?

Asked byJoshua Stockdale on 10 Sep 2021

Code Generation HDL Verifier Verification with FPGA Hardware FPGA-in-the-Loop

0

answers

0 votes
1 view

Can I used hte Spi WriteRead Block with just any SPI device or should it be only with arduino

Asked bymayur on 3 Sep 2021

Code Generation HDL Verifier Verification with FPGA Hardware FPGA-in-the-Loop

2

answers

0 votes
0 views

Does HDL Verifier support FPGA-in-the-loop for BEECube MiniBEE?

Asked byMathWorks Support Team on 21 Aug 2015

Latest activity EditedbyMathWorks Support Team on 19 Apr 2021

Accepted AnswerbyMathWorks Support Team

FPGA, ASIC, and SoC Development Vision HDL Toolbox Video Formats and Interfaces

1

answer

0 votes
0 views

Error while evaluating UIControl Callback , how pass data between fil .m and gui

Asked byfatine el amri on 30 Mar 2021

Latest activity Commented onbyfatine el amrion 31 Mar 2021

MATLAB Environment and Settings Startup and Shutdown

1

answer

0 votes
3 views

HDL Implementation of PID Controller Using FPGA-in-the-Loop

Asked byAfsher P A 2021年2月19日

Latest activity AnsweredbyAlan Moses 2021年2月22日

Accepted AnswerbyAlan Moses

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx Zynq Platform

1

answer

0 votes
1 view

Coverage in FPGA in the loop

Asked byAnder Albizu on 19 Jan 2021

Latest activity Commented onbyAnder Albizuon 1 Feb 2021

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx Zynq Platform

2

answers

0 votes
9 views

Is the Xilinx Platform Cable USB II supported for FIL simulation?

Asked byMathWorks Support Team on 9 May 2019

Latest activity Answeredbywater wateron 9 Sep 2020

Accepted AnswerbyMathWorks Support Team

Code Generation HDL Verifier Verification with FPGA Hardware FPGA-in-the-Loop

1

answer

0 votes
4 views

Using Simulink FPGA-in-the-loop (FIL) with USB3 cam and ZCU104?

Asked byTormod Njølstad on 13 Aug 2019

Latest activity AnsweredbyCharan Jadigamon 5 Mar 2020

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx Zynq Platform

3

answers

0 votes
1 view

Why can I not change the architecture of my subsystem to Black Box?

Asked bydr446 on 12 Feb 2019

Latest activity Commented onbySina Aghlion 18 Jan 2020

Code Generation HDL Verifier Verification with FPGA Hardware FPGA-in-the-Loop

1

answer

0 votes
1 view

Why do I get the error "Parameter 'instantiate_in_smartdesign' is not defined" when I try to run FIL simulation for Microsemi Polarfire board using Libero SoC v11.8?

Asked byMathWorks Support Team on 15 Oct 2019

Latest activity Commented onbyRicardo Mejia Mertelon 17 Oct 2019

Accepted AnswerbyMathWorks Support Team

Code Generation HDL Verifier Verification with FPGA Hardware FPGA-in-the-Loop

1

answer

1 vote
0 views

未能receive a control packet from the FPGA target

Asked byMedhat Elsayed on 30 Oct 2015

Latest activity AnsweredbyJazminon 13 Sep 2019

Code Generation HDL Verifier Verification with FPGA Hardware FPGA-in-the-Loop

0

answers

0 votes
0 views

Filwizard simulink model error

Asked byAbhishek Kumar on 23 May 2019

MATLAB Environment and Settings Startup and Shutdown

4

answers

0 votes
4 views

filling a matrix with a loop

Asked bybus14 on 14 May 2019

Latest activity EditedbyStephen on 16 May 2019

Accepted AnswerbyStephen

MATLAB Language Fundamentals Loops and Conditional Statements

0

answers

0 votes
0 views

Autogenerated VHDL for FPGA - In - The Loop DUT I/O Issue "** HDL Parser Error: line XX: near "vector_of_std_logic_vector32", found unsupported data-type "vector_of_std_logic_vector32""

Asked bySmattacus on 16 Mar 2018

Latest activity Commented onbymar gianon 12 May 2019

Code Generation HDL Verifier Verification with FPGA Hardware FPGA-in-the-Loop

0

answers

0 votes
0 views

ZedBoard FIL example does not run with R2018a

Asked byMike Bardill on 18 Apr 2019

Code Generation HDL Verifier Verification with FPGA Hardware FPGA-in-the-Loop

0

answers

0 votes
0 views

FPGA in the Loop for NEXYX 4 DDR

Asked byMaria Elvira Martínez de Icaya Gómez on 28 Jun 2018

Code Generation HDL Verifier Verification with FPGA Hardware FPGA-in-the-Loop

1

answer

0 votes
1 view

Why does my FIL simulation match Simulink simulation despite a timing violation in synthesis?

Asked byMathWorks Support Team on 3 Apr 2018

Latest activity AnsweredbyMathWorks Support Team on 4 Apr 2018

Accepted AnswerbyMathWorks Support Team

Code Generation HDL Verifier Verification with FPGA Hardware FPGA-in-the-Loop

2

answers

0 votes
0 views

Ethernet connexion issue with FIL programmation

Asked byMaxence Voisin on 5 May 2017

Latest activity Commented onbyMaxence Voisinon 30 Jun 2017

Accepted AnswerbyTao Jia

Code Generation HDL Verifier Verification with FPGA Hardware FPGA-in-the-Loop

1

answer

0 votes
2 views

Can I perform FPGA in the Loop with SysGen for DSP without HDL Coder and Verifier ?

Asked byYoni Levy on 9 Jun 2017

Latest activity Commented onbyYoni Levyon 14 Jun 2017

Accepted AnswerbyArnav Mendiratta

Signal Processing DSP System Toolbox Code Generation

1

answer

0 votes
5 views

FPGA is not detected during FIL on Linux

Asked byAbhishek Agrawal on 10 Mar 2017

Latest activity AnsweredbyTao Jia on 5 May 2017

Code Generation HDL Verifier Verification with FPGA Hardware FPGA-in-the-Loop

2

answers

0 votes
2 views

The Max Frequency of the signals from MATLAB to FPGA in FPGA-in-the-loop？

Asked byWENQIANG ZHANG on 11 Mar 2017

Latest activity EditedbyTao Jia on 13 Mar 2017

Accepted AnswerbyTao Jia

Code Generation HDL Verifier Verification with FPGA Hardware FPGA-in-the-Loop

0

answers

1 vote
5 views

Why I can´t get ping between a FPGA and my PC in the FPGA-in-the-Loop test?

Asked byPablo Medina on 17 Sep 2016

Code Generation HDL Verifier Verification with FPGA Hardware FPGA-in-the-Loop

0

answers

0 votes
0 views

Does anyone know what this error means? "Failed to receive a control packet from the FPGA target."

Asked byPablo Medina on 12 Sep 2016

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx Zynq Platform

1

answer

0 votes
0 views

FPGA in the loop with simulink

Asked byStefano Marano on 28 Oct 2015

Latest activity AnsweredbyJohn BGon 28 Oct 2015

Accepted AnswerbyJohn BG

MATLAB Environment and Settings Startup and Shutdown

1

answer

0 votes
0 views

Does FPGA-in-the-loop dump the VHDL code as well as provide data to the board?

Asked byMohammad Rafi Lone on 7 May 2015

Latest activity Commented onbyMohammad Rafi Loneon 8 May 2015

Accepted AnswerbyTao Jia

Code Generation HDL Verifier Verification with FPGA Hardware FPGA-in-the-Loop

1

answer

0 votes
2 views

Using FPGA in the loop setup test, getting "progamming FPGA failed" after "connect_hw_server -host localhost -port 60001"

Asked byFrank Ziegler on 1 May 2015

Latest activity AnsweredbyFrank Ziegleron 1 May 2015

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx Zynq Platform

2

answers

0 votes
1 view

HDL Parser error: Unsupported data-type sfixed in "Fpga-in-the-loop"

Asked byRaphael on 19 Mar 2013

Code Generation HDL Verifier Verification with FPGA Hardware FPGA-in-the-Loop

1

answer

0 votes
1 view

Filtering values from a curve

Asked byShalini on 26 Jan 2013

Accepted AnswerbyWayne King

MATLAB Mathematics Interpolation

0

answers

0 votes
0 views

高密度脂蛋白解析器错误DUT I/O ports specify(FPGA-in-the-Loop)

Asked byJi Man Kim on 16 Mar 2012

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx Zynq Platform

1

answer

0 votes
2 views

Digilent XUP Atlys Spartan 6 Development Board support in Hardware Co-Simulation

Asked byWilliam Knox on 25 Nov 2011

Accepted AnswerbyWilliam Knox

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx Zynq Platform

1

answer

0 votes
0 views

Using non-memory-mapped (NMM) ports with FPGA-in-the-loop (FIL) cosim with XUP Atlys Spartan 6 Dev Board

Asked byWilliam Knox on 24 Nov 2011

Accepted AnswerbyWilliam Knox

Code Generation HDL Verifier Get Started with HDL Verifier

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